• State Not Answered
  • Locked Locked
  • Replies 3 replies
  • Subscribers 93 subscribers
  • Views 5328 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Is DSU PMU supported in FVP Cortex-A73x4 A53x4 ?

XiaomingZ

Hi,

I was trying to test DSU (DynamIQ Share Unit) PMU (Performance Monitor Unit) with the example PMU_Aarch64-FVP_Cortex-A73x2-A53x4 project coming with Arm Development Studio R1.0, and I always get SyncError exception. I did modifiy the Start.S to set bit 12 of ACTLR_EL3 and ACTLR_EL2, but no help. Could anyone help on this to see why?

Thanks

Xiaoming

Parents
  • 0 Arm Employee Badge in reply to XiaomingZ

    Hi Xiaoming, I overlooked this in my earlier answer.  The Cortex-A73 and Cortex-A53 pre-date the introduction of the DSU concept.  Each cluster has it's own L1 + L2 and can snoop the other CPU's cache through a cache-coherent interconnect (e.g. CCI550).  The DSU PMU registers will therefore not be present in the FVP that you are using. 

    The DSU was first introduced with the Cortex-A75 and Cortex-A55 cores.   

Reply
  • 0 Arm Employee Badge in reply to XiaomingZ

    Hi Xiaoming, I overlooked this in my earlier answer.  The Cortex-A73 and Cortex-A53 pre-date the introduction of the DSU concept.  Each cluster has it's own L1 + L2 and can snoop the other CPU's cache through a cache-coherent interconnect (e.g. CCI550).  The DSU PMU registers will therefore not be present in the FVP that you are using. 

    The DSU was first introduced with the Cortex-A75 and Cortex-A55 cores.   

Children
No data