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Is DSU PMU supported in FVP Cortex-A73x4 A53x4 ?

Hi,

I was trying to test DSU (DynamIQ Share Unit) PMU (Performance Monitor Unit) with the example PMU_Aarch64-FVP_Cortex-A73x2-A53x4 project coming with Arm Development Studio R1.0, and I always get SyncError exception. I did modifiy the Start.S to set bit 12 of ACTLR_EL3 and ACTLR_EL2, but no help. Could anyone help on this to see why?

Thanks

Xiaoming

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0 Rob Kaye over 4 years ago in reply to XiaomingZ

Hi Xiaoming, I overlooked this in my earlier answer. The Cortex-A73 and Cortex-A53 pre-date the introduction of the DSU concept. Each cluster has it's own L1 + L2 and can snoop the other CPU's cache through a cache-coherent interconnect (e.g. CCI550). The DSU PMU registers will therefore not be present in the FVP that you are using.

The DSU was first introduced with the Cortex-A75 and Cortex-A55 cores.
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0 Rob Kaye over 4 years ago in reply to XiaomingZ

Hi Xiaoming, I overlooked this in my earlier answer. The Cortex-A73 and Cortex-A53 pre-date the introduction of the DSU concept. Each cluster has it's own L1 + L2 and can snoop the other CPU's cache through a cache-coherent interconnect (e.g. CCI550). The DSU PMU registers will therefore not be present in the FVP that you are using.

The DSU was first introduced with the Cortex-A75 and Cortex-A55 cores.
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