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RTX with External SDRAM LPC1788 - causes bus fault

Hello,

I'm using the Embedded Artists LPC1788 development kit and I'm trying to get a very simple RTX application running using the external SDRAM.

Here is what I have so far:

1) A simple RTX application that runs (blinks an LED) with no problem when I use the internal RAM. This same application crashes with a bus fault in "os_sys_init" when I us the external SDRAM.

2) I configure and initialize the external SDRAM before the call to __main (this is working as I can run the same blinking LED using the SDRAM with no RTX.

3) Even if I let me STACK and HEAP remain in the internal RAM but have variables etc.. in the SDRAM I get the bus fault.

4) The bus fault is an IMPRECISERR: Imprecise data bus error

The call stack looks like this when the fault occurs:

HardFault_Handler -> rt_put_rdy_first() -> rt_dispatch() -> rt_task_create() -> SVC_Hanlder...

Does anyone have any suggestions? I see no reason why this should cause a fault.

Thanks.

MAC

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  • Hi Dave,

    When the CPU clock divider is 1 than this will calculate correctly. The problem is when it isn't.

    This is what I believe is required as a change:

    #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
    #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
    #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
    

    The reason is that the fig. 7 in the user manual is incorrect. The EMC Clock divider is not feed from the mux (sys_clk or pll0_clk) it is feed from the CPU clock.

    So in your setup if you divided the CPU clock to 60MHz (by 2) the EMC Clock would still calculate to 120MHz which is incorrect.

    Hope this helps.

    Regards,

    Marc

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  • Hi Dave,

    When the CPU clock divider is 1 than this will calculate correctly. The problem is when it isn't.

    This is what I believe is required as a change:

    #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
    #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
    #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
    

    The reason is that the fig. 7 in the user manual is incorrect. The EMC Clock divider is not feed from the mux (sys_clk or pll0_clk) it is feed from the CPU clock.

    So in your setup if you divided the CPU clock to 60MHz (by 2) the EMC Clock would still calculate to 120MHz which is incorrect.

    Hope this helps.

    Regards,

    Marc

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