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RTX with External SDRAM LPC1788 - causes bus fault

Hello,

I'm using the Embedded Artists LPC1788 development kit and I'm trying to get a very simple RTX application running using the external SDRAM.

Here is what I have so far:

1) A simple RTX application that runs (blinks an LED) with no problem when I use the internal RAM. This same application crashes with a bus fault in "os_sys_init" when I us the external SDRAM.

2) I configure and initialize the external SDRAM before the call to __main (this is working as I can run the same blinking LED using the SDRAM with no RTX.

3) Even if I let me STACK and HEAP remain in the internal RAM but have variables etc.. in the SDRAM I get the bus fault.

4) The bus fault is an IMPRECISERR: Imprecise data bus error

The call stack looks like this when the fault occurs:

HardFault_Handler -> rt_put_rdy_first() -> rt_dispatch() -> rt_task_create() -> SVC_Hanlder...

Does anyone have any suggestions? I see no reason why this should cause a fault.

Thanks.

MAC

Parents

0 David Brooks over 13 years ago in reply to @Marc Crandall

Hi Marc,

I took a look at the definition for EMCClock, and this is what I found:

uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */

tracing the definition for __EMC_CLK further reveals this:

  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
                #define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
        #define __EMC_CLK  (IRC_OSC/  __ECLK_DIV)
    #else                               /* sysclk = osc_clk */
        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
        #define __EMC_CLK  (OSC_CLK/  __ECLK_DIV)
    #endif
  #else                                 /* cclk = pll_clk */
    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
        #define __EMC_CLK  (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
    #else                               /* sysclk = osc_clk */
        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
        #define __EMC_CLK  (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
    #endif
  #endif

When this is evaluated at compile time, since I'm using the PLL0 clock, and my sysclk is the osc_clk, I get simply:

      #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
      #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
      #define __EMC_CLK  (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)

evaluating the macro __PLL0_CLK(), I get:

#define __M                   ((PLL0CFG_Val & 0x1F) + 1)
#define __PLL0_CLK(__F_IN)    (__F_IN * __M)

Since OSC_CLK is defined as XTAL, which is 12M, and __PLL0_CLK(12M) = 120M (since __M = 10 for me), the __EMC_CLK value is calculated correctly (I believe).

Can you please explain this better for me?

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