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CTRLSTAT = 0xffffffff

harshan

Sir,

I am working on Cortex-M4 over serial wire debug protocol, i am able to read IDCODE(0x2ba01477) which is correct as per arm cortex m4 technical reference manual, and i am writing 0x50000000 to CTRLSTAT register to enable CSYSPWRUPREQ and CDBGPWRREQ which is also success without any ACK error,but the thing is when i am trying to read the CTRLSTAT register i got 0xffffffff . I don't understand what might be the problem,Please suggest me what would be the problem??

Thanks & Regards

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  • 0 in reply to harshan

    The timing information can be found on the ARM Information Center under SWD timing requirements.

    Each edge should be between 10 ns and 500 us.

    That means ... If you're running at 168MHz: at least 2 clock cycles (one for writing, one for delay), maximum 84000 clock cycles.

    I think you can use something like this, in order to get the fastest possible transfer rate at 168MHz:

    #define SW_NOP      __NOP()

    #define SWDIO_HI    /* replace this comment with a way to set the SWDIO pin high */

    #define SWDIO_LO    /* replace this comment with a way to set the SWDIO pin low */

    #define SWDIO_IN    /* replace this comment with a way to read the SWDIO pin; the value should be either 1 or 0 */

    #define SWDIO_(b)   if(b){ SWDIO_HI; } else { SWDIO_LO; }

    #define WR(b)       SWDIO_(b) ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    #define WR1         SWDIO_HI  ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    #define WR0         SWDIO_LO  ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    #define RD          SW_NOP    ; SWCLK_LO ; bit = SWDIO_IN ; SW_CLK_HI

    #define CLK         SW_NOP    ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    The CLK macro can be used to repeat a bit; eg. if you know you're outputting 8 zero bits, you can issue WR0; CLK; CLK; CLK; CLK; CLK; CLK; CLK.

    Note: The order of reading and writing must match exactly, and the high and low states on the clock must also be exact.

    (That does not mean that I've written the above code correctly, though).

    The WR1 would take one clock cycle, if it's translated into a STR instruction without loading register values first.

    The WR0 would also take one clock cycle (same case).

    The RD might take two or three clock cycles, because it's often necessary to perform a bitwise AND operation before using a bitwise OR operation to insert the new bit into a register.

    The assembly code would usually look like this:

                        ldr                 r2,[r3]             /* [2] read the pin state */

                        and                 r2,r1,r2,lsr#4      /* [1] move bit 4 to bit 0 and isolate it, so it's now either 0 or 1 /*

                        add                 r0,r2,r0,ror#1      /* [1] shift the result right by 1, then insert the new bit */

    Using the above mehtod means that after receiving all the bits, you'd need to rotate the entire result left by the number of bits received -  1.

    Note: on Cortex-M4, the BFX instruction can also be used for extracting the bit.

    -But in some cases, you might be able to read from a port, where the bit value will always be 1 or 0.

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  • 0 in reply to harshan

    The timing information can be found on the ARM Information Center under SWD timing requirements.

    Each edge should be between 10 ns and 500 us.

    That means ... If you're running at 168MHz: at least 2 clock cycles (one for writing, one for delay), maximum 84000 clock cycles.

    I think you can use something like this, in order to get the fastest possible transfer rate at 168MHz:

    #define SW_NOP      __NOP()

    #define SWDIO_HI    /* replace this comment with a way to set the SWDIO pin high */

    #define SWDIO_LO    /* replace this comment with a way to set the SWDIO pin low */

    #define SWDIO_IN    /* replace this comment with a way to read the SWDIO pin; the value should be either 1 or 0 */

    #define SWDIO_(b)   if(b){ SWDIO_HI; } else { SWDIO_LO; }

    #define WR(b)       SWDIO_(b) ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    #define WR1         SWDIO_HI  ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    #define WR0         SWDIO_LO  ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    #define RD          SW_NOP    ; SWCLK_LO ; bit = SWDIO_IN ; SW_CLK_HI

    #define CLK         SW_NOP    ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

    The CLK macro can be used to repeat a bit; eg. if you know you're outputting 8 zero bits, you can issue WR0; CLK; CLK; CLK; CLK; CLK; CLK; CLK.

    Note: The order of reading and writing must match exactly, and the high and low states on the clock must also be exact.

    (That does not mean that I've written the above code correctly, though).

    The WR1 would take one clock cycle, if it's translated into a STR instruction without loading register values first.

    The WR0 would also take one clock cycle (same case).

    The RD might take two or three clock cycles, because it's often necessary to perform a bitwise AND operation before using a bitwise OR operation to insert the new bit into a register.

    The assembly code would usually look like this:

                        ldr                 r2,[r3]             /* [2] read the pin state */

                        and                 r2,r1,r2,lsr#4      /* [1] move bit 4 to bit 0 and isolate it, so it's now either 0 or 1 /*

                        add                 r0,r2,r0,ror#1      /* [1] shift the result right by 1, then insert the new bit */

    Using the above mehtod means that after receiving all the bits, you'd need to rotate the entire result left by the number of bits received -  1.

    Note: on Cortex-M4, the BFX instruction can also be used for extracting the bit.

    -But in some cases, you might be able to read from a port, where the bit value will always be 1 or 0.

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