CTRLSTAT = 0xffffffff

,

after writing into flash  if i am trying to  reading from the flash address i got 0xffffffff i don't know why that happening ??

Thanks & Regards.

,

after writing into flash  if i am trying to  reading from the flash address i got 0xffffffff i don't know why that happening ??

Thanks & Regards.

Thanks for Reply sir,

                              in above post you wrote "0x40023c04=0x45670123. 0x4002c304=0xcdef89ab" hear both addresses are different , in stm32f4 reference manual  3.6.1 he mentioned that both keys 0x45670123 and 0xcdef89ab should be send to FLASH_KEYR(0x40023C04) register please make a clarity on that and another thing is my flash Unlock was unsuccess full.

my procedure was

halt

reset

reading status of FLASH_CR register if LOCK bit is set then

sending 0x45670123 and 0xcdef89ab  to FLASH_KEYR register.

delay: for loop ->1000

then reading status of FLASH_CR register.

Thanks and Regards.

Most likely your Flash memory is protected.

It's important that you know there are two unlock sequences.

First you will need to check that the LOCK bit of FLASH_CR is zero. If it is not zero, you will want to unlock it by sending the unlock sequence mentioned earlier:

0x40023c04=0x45670123. 0x40023c04=0xcdef89ab.

Then you may need to wait for a few milliseconds; I do not know how long, but try giving it a good delay at first, then you can reduce it and see when it fails.

Now read FLASH_SR first. It is important to check all the things in this register that can go wrong. In particular, we're interested in bit 4, the WRPERR bit.

-If the WRPERR bit is set, we're in trouble, but we'll also need to be free of other errors.

If there are no errors, however, then we can proceed and read FLASH_CR again, to verify that the LOCK bit is now zero.

If the LOCK bit of FLASH_CR is zero, then we can proceed.

Read the FLASH_OPTCR register. by reading address 0x40023c14. If this register does not contain 0x0fffaae1, then you'll most likely get write protection errors in FLASH_SR after attempting to write to the flash-memory.

So if FLASH_OPTCR register's bits 27:16 are not all 1, then we'll need to modify them. Bits 15:8 must be 0xaa. So we'll write the following:

0x40023c08=0x08192a3b. 0x40023c08=0x4c5d6e7f. 0x40023c14=0x0fffaaed.

Right after that sequence, we should read FLASH_SR, to check for errors.

Then read FLASH_CR and verify that the LOCK bit is still zero.

After that, we should read the FLASH_OPTCR register, to verify that the value is now changed; expect 0x0fffaae1.

OK, we're about to flash-program the device, so now we'll do the checking again.

Read the FLASH_OPTCR register (address 0x40023c14), if bits 27:16 are not all ones, we can't write to the flash-memory.

Now read FLASH_SR, and verify that there were no error reading FLASH_OPTCR.

Finally, read FLASH_CR and verify that the LOCK bit is still zero (I expect that it always is zero).

If all checks out, try writing a block of data to the Flash memory.

Right after writing the last 32-bit word of your data block, you should immediately read FLASH_SR and check for any errors.

If bit 4 is set, then you could not write to the flash memory, because it's write-protected (somehow that means that the FLASH_OPTCR does not contain the value we'd expect by now).

If any of the above sequences do not contain the values I wrote, please let me know, I could have made a typo.

I'm sorry, 0x4002c304 was a typo, I believe the right address should be 0x40023c04.

Did you try reading FLASH_SR right after writing the two values to FLASH_KEYR ?

What are the values you read from FLASH_SR and FLASH_CR ?

thank you for suggestion,

after sending the key to FLASH_KEYR register

reading

FLASH_CR = 0x80000000

FLASH_SR = 0x000000c0

Thanks & regards.

Hmm, at least you can read the registers.

I'm about to run out of ideas, but maybe it will help, if you try inserting dummy-clocks (for instance 50 zero-bits) between writing the unlocking-sequence, like this:

Write the first word, send 50 dummy-clocks, write the second word, send 50 dummy-clocks, read CR, read CR.

thanks for quick reply,

i got error resolved, the problem is each time while writing i selcting CSW register, with out that i wrote the following sequence

setting CSW register with proper bit settings then

TAR = FLASH_KEYR

DRW = KEY1

idle cycle

TAR = FLASH_KEYR

DRW = KEY2

idle cycle

now i am reading

FLASH_CR = 0x00000000

FLASH_SR = 0x000000C0

after above

i wrote data to flash memory as following procedure

checking BSY bit in FLASH_SR register wait until this bit is cleared.

setting PG bit and 32bit selection by

FLASH_CR = 0x00000201

after that I am trying to read the FLASH_CR and FLASH_SR register

but i got as following

FLASH_CR = 0x00000000

FLASH_SR = 0x000000C0

data is not updated on FLASH_CR register???

my doubt is after halt and reset no registers are modified why??

Try writing 0x00000200 first, then 0x00000201.

For instance:

read 0x40023c0c  (FLASH_SR)

read 0x40023c10 (FLASH_CR)

0x40023c10 = 0x00000200;

read 0x40023c0c  (FLASH_SR)

read 0x40023c10 (FLASH_CR)

0x40023c10 = 0x00000201;

read 0x40023c0c  (FLASH_SR)

read 0x40023c10 (FLASH_CR)

-But before that, I think it would be a good idea to read FLASH_OPTCR (0x40023c14) and check that it allows you to write to the Flash-memory.

This could also be a power issue. Make sure VOS in PWR_CR is set to Scale1 mode. (there's also a VOS_RDY bit you'll have to wait for)

thank you sir,

                    i tried your above approach i got FLASH_OPTCR = 0x0FFFAAED , and PWR_CR = 0x0000C000. is there any wrong with these values??

Thanks & Regards,

I just looked in the sources for the stlink tool. This might bring you to the solution.

In the file "stlink-common.c", line 1593 ...

After the sequence you mentioned, it writes a small piece of code into the SRAM and executes it.

This piece of code copies a data block from the address that register r0 points to, to the address that register r1 points to, the length of the data block is r2 bytes.

So this small piece of code can be used for both reading flash memory and writing flash memory.

In the same file, line 1765, you'll find the routine (run_flash_loader) that sets the parameters and runs the piece of code in SRAM.

The routine, which sets the value of a core register is also interesting, it's called stlink_write_reg, and is actually located in stlink-usb.c as _stlink_usb_write_reg at line 680.

Thank you sir,

                      I found the bug and fixed it, the bug was i have to check each time whether BSY bit in FLASH_SR was set or not that makes the consistency. Thank you for your valuable suggestions and support

Thanks & Regards,

harshan

Excellent news. Thank you for letting us know and also that you kept going when it wasn't easy.

I am very convinced that this will be valuable help for anyone who implements the SWD protocol in their own applications.

hi sir,

          may i know where could i found detailed explanation about watch points and break points ?? in reference manual he given a little bit but i need in programmer view where could i get such information??

Thanks & Regards.