Hi experts,
I'm using a Juno r1 board for some cache-related research experiment so I'm studying the related memory attributes such as cacheability and shareability.
I found the manual mentioned that: " the division between inner and outer is IMPLEMENTATION DEFINED".
However, I tried to search the answer in the juno manual while I don't find any detailed definition about the inner / outer domains?
Does anyone know how to find these concepts for Juno?
Thank you in advance.
Simon
Hi Simon,
From a purely hardware perspective, the inner shareable domain on Juno comprises the A-class processors, the Mali T-624 GPU, and PCIe.
Note that the Mali T-624 GPU and PCIe are connected to ACE-Lite slave ports on the interconnect, meaning they can snoop into the A-class processor caches but they themselves *cannot* be snooped.
For future reference: the AArch64 CLIDR_EL1.LoUIS field indicates the inner shareable level of unification of the processor's cache hierarchy; for the Cortex-A53 and Cortex-A72 this is 0b1, corresponding to the L2 cache. This means anything stored in the A-class processor integrated caches up to and including the L2 caches will be visible to anything in the inner shareable domain, and that you'll need to clean out past L2 (i.e. to main memory) for data to be visible to outer shareable entities.
CLIDR_EL1.LoUIS
0b1
Hope that helps.
Hi, I think that for Juno... wrt the cache settings: The L1/L2 CPU caches are going to be inner and there is no outer system cache (in the interconnect) for Juno. wrt shareability: the interconnect (CCI-400) doesn't differentiate between inner & outer. But, the bL system is effectively in a single inner shareable domain. FWIW Linux only supports inner shareable mappings by default. HTH MarkN.