Please note: We are aware of an issue affecting replies on the Arm Community forums, which may not be loading as expected.
We apologize for any inconvenience and appreciate your patience while we investigate and work to resolve the issue.
Thank you for your understanding.
Hi experts,
I'm using a Juno r1 board for some cache-related research experiment so I'm studying the related memory attributes such as cacheability and shareability.
I found the manual mentioned that: " the division between inner and outer is IMPLEMENTATION DEFINED".
However, I tried to search the answer in the juno manual while I don't find any detailed definition about the inner / outer domains?
Does anyone know how to find these concepts for Juno?
Thank you in advance.
Simon
Hi, I think that for Juno... wrt the cache settings: The L1/L2 CPU caches are going to be inner and there is no outer system cache (in the interconnect) for Juno. wrt shareability: the interconnect (CCI-400) doesn't differentiate between inner & outer. But, the bL system is effectively in a single inner shareable domain. FWIW Linux only supports inner shareable mappings by default. HTH MarkN.