Juno r1 Shareability Memory Attributes

Hi Shengye,

I don't know Juno.r1 has chosen which. But I know `IMPLEMENTATION DEFINED` means[1]. It's defined by the manufacturer. In case of Juno, ARM is the manufacturer.


[1] Glossary
IMPLEMENTATION DEFINED:
Some properties of the processor are defined by the manufacturer

Hi John,

Thank you for the reply. I found this IMPLEMENTATION DEFINED definition later yesterday too :)
I hope somebody of ARM could tell me the clear definition of inner/outer domain of Juno r1.

Hi Simon,

From a purely hardware perspective, the inner shareable domain on Juno comprises the A-class processors, the Mali T-624 GPU, and PCIe.

Note that the Mali T-624 GPU and PCIe are connected to ACE-Lite slave ports on the interconnect, meaning they can snoop into the A-class processor caches but they themselves *cannot* be snooped.

For future reference: the AArch64 CLIDR_EL1.LoUIS field indicates the inner shareable level of unification of the processor's cache hierarchy; for the Cortex-A53 and Cortex-A72 this is 0b1, corresponding to the L2 cache. This means anything stored in the A-class processor integrated caches up to and including the L2 caches will be visible to anything in the inner shareable domain, and that you'll need to clean out past L2 (i.e. to main memory) for data to be visible to outer shareable entities.

Hope that helps.

Hi, I think that for Juno...

wrt the cache settings: The L1/L2 CPU caches are going to be inner and there is no outer system cache (in the interconnect) for Juno.

wrt shareability: the interconnect (CCI-400) doesn't differentiate between inner & outer. But, the bL system is effectively in a single inner shareable domain. FWIW Linux only supports inner shareable mappings by default.

HTH
MarkN.