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Could someone suggest a way to change the boot value of a control register (e.g. ACTLR)? It seems like i'd want to do it in bl31:bl31_arch_setup(), but does each CPU go through bl31 or just the boot CPU? If I was just interested in the A7s is there a way to only boot them?
Thanks,
Ali
I have a few more questions. If I only want to boot the the A53 cores then I'd write the following?
SCC: 0x0F4 0x000000F0
Not quite, without bit 3 (Boot Map) set, the Boot Map mechanism is disabled and the SCP releases by default only Cortex-A53_0. To release only the Cortex-A53 cluster you would need the following (this would set the primary CPU as A53_0 also).
SCC: 0x0F4 0x000000F8
Does bl31_arch_setup() get called for each core, or just the boot core?
Yes.
See description in:
arm-trusted-firmware/bl31/aarch64/bl31_arch_setup.c at master · ARM-software/arm-trusted-firmware · GitHub
Hi Luke,
I added the following lines to boards.txt however all CPUs (A57 and A53) still booted:
[SCC REGISTERS]
TOTALSCCS: 1
Does something have to be done for the vesatile express to re-process the boards.txt file?
P.S. modifying bl31_arch_setup() did the trick. Thanks again!
The SCC register defines which CPUs the SCP will release from reset. You should be able to see the Cortex-A57 cluster is powered down if you stop the boot in UEFI (pressing any key). It seems that the Linux kernel is bringing up the Cortex-A57 cores during the kernel boot. I just performed a quick test, in which I removed the reference to the Cortex-A57 cores in the DST file (then compile the new DTB). This seems to do the trick. I assume there's a more elegant way to do this.
If this has answered your questions, can you please mark this as Correct.
Thanks again for all of your help Luke!
Hi Asaidi,
I think along with the precise changes suggested by Luke we need to also modify the kernel config option NR_CPUS to 4 as well to avoid any unnecessary data structure initialization during the Linux kernel boot up.
Great Answer Luke!