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Could someone suggest a way to change the boot value of a control register (e.g. ACTLR)? It seems like i'd want to do it in bl31:bl31_arch_setup(), but does each CPU go through bl31 or just the boot CPU? If I was just interested in the A7s is there a way to only boot them?
Thanks,
Ali
The SCC General Purpose Register 1 (SCC GPR1) can be used to determine the boot CPUs. The layout of SCC GPR1 is as follows:
0 - Crypto Disable
1 - CFGTE
2 - CFGEE
3 - Boot Map Enable (default = 0)
4 - A53-0
5 - A53-1
6 - A53-2
7 - A53-3
8 - A57-0
9 - A57-1
10 - Reserved
11 - Reserved
[15:12] - Primary CPU selection. Index values 0 through 5, following
the order of cores above.
To set the Cortex-A57 as the boot cluster and Cortex-A57_0 as the primary CPU you will need to set bit 3 to enable the boot map, set bits 8,9 to select the A57s and finally setting [15:12] to 0x4 so that Cortex-A57_0 is considered the primary CPU. You will need to add the following SCC entry to the 'board.txt' file located in "E:\SITE1\HBI0262B":
SCC: 0x0F4 0x00004308 ;
This will determine what CPUs are brought out of reset by the SCP. This said, the AP Trusted firmware was hardcoded to use Cortex-A53_0 as the primary CPU.
To change the primary CPU in the AP Trusted Firmware, the PRIMARY_CPU entry in 'plat/juno/platform.h' will need to be altered. Steps describing how to re-build the AP Trusted firmware can be found on the 'Juno Software Guide ' page.
Regarding where system configurations such as setting the ACTLR should be performed, we would recommend either cpu_reset_handler() in BL1 or it can be done in bl31_arch_setup().
Thanks Luke!
I have a few more questions. If I only want to boot the the A53 cores then I'd write the following?
SCC: 0x0F4 0x000000F0
Does bl31_arch_setup() get called for each core, or just the boot core?
Thanks again,
Not quite, without bit 3 (Boot Map) set, the Boot Map mechanism is disabled and the SCP releases by default only Cortex-A53_0. To release only the Cortex-A53 cluster you would need the following (this would set the primary CPU as A53_0 also).
SCC: 0x0F4 0x000000F8
Yes.
See description in:
arm-trusted-firmware/bl31/aarch64/bl31_arch_setup.c at master · ARM-software/arm-trusted-firmware · GitHub
Hi Luke,
I added the following lines to boards.txt however all CPUs (A57 and A53) still booted:
[SCC REGISTERS]
TOTALSCCS: 1
Does something have to be done for the vesatile express to re-process the boards.txt file?
P.S. modifying bl31_arch_setup() did the trick. Thanks again!
The SCC register defines which CPUs the SCP will release from reset. You should be able to see the Cortex-A57 cluster is powered down if you stop the boot in UEFI (pressing any key). It seems that the Linux kernel is bringing up the Cortex-A57 cores during the kernel boot. I just performed a quick test, in which I removed the reference to the Cortex-A57 cores in the DST file (then compile the new DTB). This seems to do the trick. I assume there's a more elegant way to do this.
If this has answered your questions, can you please mark this as Correct.
Thanks again for all of your help Luke!
If multiple cpu booted, they work in SMP mode in default? luked
Hi Asaidi,
I think along with the precise changes suggested by Luke we need to also modify the kernel config option NR_CPUS to 4 as well to avoid any unnecessary data structure initialization during the Linux kernel boot up.
Great Answer Luke!