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The problem of modifying the cache parameter in the Canvas

I want to modify cache latency parameter in system canvas,and I use FVP_Base_Neoverse-N1 to build my system,so is it correct to modify the cache parameters like this?

Parents
  • Hi Rob

    I have another problem now.

    I set cache_state_modelled=1,dcache-state_modelled=1,icache-state_modelled=1,dcache-hit_latency=0x4,cpu0.l2cache-hit_latency=0x10 in LISA, and build,then I set environment value FASTSIM_DISABLE_TA="0". Then start FVP.

    I use lmbench to test the fixed model on FVP, Lmbench is a miniature assessment tool(link is here: http://www.bitmover.com/lmbench/), and I use lat_mem_rd(memory read latency benchmark) to get mem_load_latency(link is here: http://www.bitmover.com/lmbench/lat_mem_rd.8.html). The memory size of the test is set to 128MB, but the result of mem-load-latency test is always about 10ns, the fixed parameter seems to be not enable.

    The test file is here,the first column is the memory range, and the second column is the mem_load_latency.

    Memsize	latencytime
    0.00049	10.729
    0.00098	10.719
    0.00195	10.719
    0.00293	10.72
    0.00391	10.72
    0.00586	10.72
    0.00781	10.72
    0.00977	10.72
    0.01172	10.72
    0.01367	10.563
    0.01562	10.565
    0.01758	10.566
    0.01953	10.567
    0.02148	10.565
    0.02344	10.567
    0.02539	10.512
    0.02734	10.513
    0.0293	10.516
    0.03125	10.514
    0.03516	10.514
    0.03906	10.487
    0.04297	10.487
    0.04688	10.486
    0.05078	10.472
    0.05469	10.472
    0.05859	10.473
    0.0625	10.462
    0.07031	10.462
    0.07812	10.457
    0.08594	10.45
    0.09375	10.449
    0.10156	10.444
    0.10938	10.445
    0.11719	10.442
    0.125	10.437
    0.14062	10.435
    0.15625	10.434
    0.17188	10.431
    0.1875	10.429
    0.20312	10.428
    0.21875	10.427
    0.23438	10.426
    0.25	10.425
    0.28125	10.423
    0.3125	10.422
    0.34375	10.423
    0.375	10.419
    0.40625	10.419
    0.4375	10.419
    0.46875	10.418
    0.5	10.418
    0.5625	10.417
    0.625	10.416
    0.6875	10.416
    0.75	10.416
    0.8125	10.416
    0.875	10.414
    0.9375	10.413
    1	10.415
    1.125	10.417
    1.25	10.415
    1.375	10.415
    1.5	10.411
    1.625	10.416
    1.75	10.415
    1.875	10.414
    2	10.412
    2.25	10.412
    2.5	10.414
    2.75	10.412
    3	10.411
    3.25	10.415
    3.5	10.413
    3.75	10.411
    4	10.412
    4.5	10.411
    5	10.415
    5.5	10.414
    6	10.412
    6.5	10.414
    7	10.412
    7.5	10.413
    8	10.414
    9	10.413
    10	10.413
    11	10.408
    12	10.41
    13	10.415
    14	10.414
    15	10.411
    16	10.415
    18	10.413
    20	10.413
    22	10.411
    24	10.412
    26	10.411
    28	10.412
    30	10.411
    32	10.414
    36	10.411
    40	10.412
    44	10.412
    48	10.41
    52	10.411
    56	10.411
    60	10.411
    64	10.412
    72	10.409
    80	10.413
    88	10.412
    96	10.41
    104	10.411
    112	10.412
    120	10.412
    128	10.412
    

Reply
  • Hi Rob

    I have another problem now.

    I set cache_state_modelled=1,dcache-state_modelled=1,icache-state_modelled=1,dcache-hit_latency=0x4,cpu0.l2cache-hit_latency=0x10 in LISA, and build,then I set environment value FASTSIM_DISABLE_TA="0". Then start FVP.

    I use lmbench to test the fixed model on FVP, Lmbench is a miniature assessment tool(link is here: http://www.bitmover.com/lmbench/), and I use lat_mem_rd(memory read latency benchmark) to get mem_load_latency(link is here: http://www.bitmover.com/lmbench/lat_mem_rd.8.html). The memory size of the test is set to 128MB, but the result of mem-load-latency test is always about 10ns, the fixed parameter seems to be not enable.

    The test file is here,the first column is the memory range, and the second column is the mem_load_latency.

    Memsize	latencytime
    0.00049	10.729
    0.00098	10.719
    0.00195	10.719
    0.00293	10.72
    0.00391	10.72
    0.00586	10.72
    0.00781	10.72
    0.00977	10.72
    0.01172	10.72
    0.01367	10.563
    0.01562	10.565
    0.01758	10.566
    0.01953	10.567
    0.02148	10.565
    0.02344	10.567
    0.02539	10.512
    0.02734	10.513
    0.0293	10.516
    0.03125	10.514
    0.03516	10.514
    0.03906	10.487
    0.04297	10.487
    0.04688	10.486
    0.05078	10.472
    0.05469	10.472
    0.05859	10.473
    0.0625	10.462
    0.07031	10.462
    0.07812	10.457
    0.08594	10.45
    0.09375	10.449
    0.10156	10.444
    0.10938	10.445
    0.11719	10.442
    0.125	10.437
    0.14062	10.435
    0.15625	10.434
    0.17188	10.431
    0.1875	10.429
    0.20312	10.428
    0.21875	10.427
    0.23438	10.426
    0.25	10.425
    0.28125	10.423
    0.3125	10.422
    0.34375	10.423
    0.375	10.419
    0.40625	10.419
    0.4375	10.419
    0.46875	10.418
    0.5	10.418
    0.5625	10.417
    0.625	10.416
    0.6875	10.416
    0.75	10.416
    0.8125	10.416
    0.875	10.414
    0.9375	10.413
    1	10.415
    1.125	10.417
    1.25	10.415
    1.375	10.415
    1.5	10.411
    1.625	10.416
    1.75	10.415
    1.875	10.414
    2	10.412
    2.25	10.412
    2.5	10.414
    2.75	10.412
    3	10.411
    3.25	10.415
    3.5	10.413
    3.75	10.411
    4	10.412
    4.5	10.411
    5	10.415
    5.5	10.414
    6	10.412
    6.5	10.414
    7	10.412
    7.5	10.413
    8	10.414
    9	10.413
    10	10.413
    11	10.408
    12	10.41
    13	10.415
    14	10.414
    15	10.411
    16	10.415
    18	10.413
    20	10.413
    22	10.411
    24	10.412
    26	10.411
    28	10.412
    30	10.411
    32	10.414
    36	10.411
    40	10.412
    44	10.412
    48	10.41
    52	10.411
    56	10.411
    60	10.411
    64	10.412
    72	10.409
    80	10.413
    88	10.412
    96	10.41
    104	10.411
    112	10.412
    120	10.412
    128	10.412
    

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