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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    How to check whether the executing program uses cache memory for low latency? 0

    17704 views
    1 reply
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    How does the memory regions are mapped in A72 cortex? 0

    18644 views
    2 replies
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    L2 cache error injection and Prefetch Abort 0

    16645 views
    1 reply
    Latest over 5 years ago
    by XNoOp
  • Not Answered

    Penalty estimate of TLB miss or table walk in armv8 0

    17295 views
    2 replies
    Latest over 5 years ago
    by XNoOp
  • Suggested Answer

    STM32H745 dual-core debugging with IAR toolchain 0

    • Cortex-M7
    • stm32 h7
    • Cortex-M
    • Debugger
    • Cortex-M4
    4562 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Seeking more information on SError on A53 core 0

    18773 views
    2 replies
    Latest over 5 years ago
    by KPK
  • Not Answered

    Why L1 cache associativity DOUBLED and index method CHANGED from the programmer's point of view? 0

    • Cache
    18289 views
    4 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    IRQ Execution in nRF51 0

    • Cortex-M0
    3395 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Answered

    Question about PMU in detail 0

    17929 views
    3 replies
    Latest over 5 years ago
    by zilly
  • Suggested Answer

    SPI1 CMSIS STM32F407VG 0

    • STM32F4DISCOVERY
    • CMSIS
    3072 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Play a wav file from an SD card 0

    4914 views
    7 replies
    Latest over 5 years ago
    by Andy Neil
  • Suggested Answer

    How to report typo in Cortex M4 Generic User Guide? 0

    2297 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Suggested Answer

    Input capture problem 0

    3024 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    AXI WR_STRB=0's when WVALID =1. 0

    17567 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    How generic are Cortex-M0+ MCUs? 0

    • Toolchain
    • Cortex-M0
    • Cortex-M0+
    3017 views
    2 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    CMSIS-DSP on ARMv8-m 0

    • Digital Signal Processor (DSP)
    • Armv8-M
    • CMSIS
    3484 views
    1 reply
    Latest over 5 years ago
    by trembel
  • Answered

    fixed Burst 0

    4680 views
    2 replies
    Latest over 5 years ago
    by tom
  • Not Answered

    What is difference between DCCIMVAC and DCIMVAC? 0

    • Cache coherency
    • Armv8-A
    21464 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Mapping of AXI cache with AHB5 prot 0

    18024 views
    0 replies
    Started over 5 years ago
    by Manasa Avula
  • Answered

    Performance ratio between A35 and M4 0

    • Cortex-A35
    • Cortex-M4
    18970 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
<>
Topics being discussed in this forum
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