• State Not Answered
  • Locked Locked
  • Replies 1 reply
  • Subscribers 350 subscribers
  • Views 17545 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

A72 Invalidate dirty cache line (DC IVAC)

uFedor

The A53 TRM says that when you invalidate a dirty cache line (DC IVAC), then a clean is automatically performed before the invalidate.

Does the A72 have the same behavior?

Is it possible to invalidate a dirty cache line without the clean happening?

  • 0

    ARM.ARM says:

    <quote>

    When executed at EL1, a DC IVAC instruction performs a clean and invalidate, meaning it performs the same
    maintenance as a DC CIVAC instruction, if all of the following apply:
    • EL2 is implemented and enabled in the current Security state.
    • The value of HCR_EL2.VM is 1, meaning EL1&0 stage two address translation is enabled.

    </quote>

    So I think it is impossible to invalidate a dirty cache line without the cleaning.