Priority Drop and Deactivation Interrupts at EL2

Hello 

I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage

I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2  using these piece of code 

MRS X0, HCR_EL2
AND X0, X0, 0xFFFFFFFFF7FFFFFF
ORR X0, X0, 0x0000000000000038
MSR HCR_EL2, X0

when it comes to the interrupt activation, priority drop and deactivation the in IHI0069F it says in chapter 4.1.1 Activation 

Activation

"The interrupt handler reads ICC_IAR0_EL1 for Group 0 interrupts, and ICC_IAR1_EL1 for Group 1 interrupts, in
the corresponding CPU interface to acknowledge the interrupt"

Priority Drop

"After an interrupt has been acknowledged, a valid write to ICC_EOIR0_EL1 for Group 0 interrupts, or a valid write
to ICC_EOIR1_EL1 for Group 1 interrupts, results in a priority drop."

so the question is there a relative registers to do the same function at EL2 ?

Or is there a whole different configuration when working in EL2 for the GIC and the CPU_Inteface?