Hi,
I am university student at my final year and I am doing research on Cortex-M3.
One thing that I found problematic was system bus registration of instruction and vector fetch requests.Only available source of information I found was this paragraph in documentation, but it wasn't descriptive enough.
I am not sure what is registered and when. Is it address, response or maybe both of them?I would be grateful if somebody could point me to more descriptive material.
Yes. Essentially it provides a clean timing interface by registering this interface. So there is an additional cycle by including the register in the interface pathway. So fetching vectors /instructions incurs an additional pathway. For the CM3 the recommendation is to have code via the I-code interface for this reason. This was done to ensure implementation on the backend is easier to meet timing.
Thank you for response.
Do you know how exactly it works?> What is registered and when. Is it address, response or maybe both of them?