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Cortex M33 Tracing

Lica over 5 years ago

Hey,

As I am exploring the tracing capabilities present in the Cortex M33, there are some things that I am not able to understand fully, such as the connection between ETM and the tracing sinks. As I read, more doubts emerged, and the more confused I got. So what I wanted to know is:

Is it possible to access the tracing streams from the running system? What I mean is if the core can obtain these packets while running.
What is the difference between the Micro Trace Buffer(MTB) and Embedded Trace Buffer(ETB)? I thought both acted like buffers for the trace packets generated by a tracing unit, such as the ETM.

Cheers

0 42Bastian Schick over 5 years ago

ETB - Buffer in the Trace Cell
MTB - Interface to the SoC SRAM (depends on the SoC where it goes).
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0 Lica over 5 years ago in reply to 42Bastian Schick

Hey again,

Thanks for your reply! So one question remains. Can the host/running Core access the Embedded Trace Buffer? As much as I searched, I can`t find any memory mapping for the ETB. Thus that means that it is only accessible by a debug probe to download the trace data?

Note: I am using a board that implements the Arm CoreLink SSE-200 subsystem.

Cheers
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0 Mark196 over 5 years ago in reply to Lica

I don't thing it can access. Bcoz it can damage the entire system then UPSers
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0 42Bastian Schick over 5 years ago in reply to Lica

Etb can be read.
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0 42Bastian Schick over 5 years ago in reply to Mark196

Why should it damage anything?
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0 Lica over 5 years ago in reply to 42Bastian Schick
To clarify, I found that the ETB is not implemented on the board that I am using. Thank you all for the answers.

Just another question that I am wondering. The comparators on the DWT unit are connected? If so, how? I am trying to watch accesses of a specific region of memory, and from what I tried, I got no kind of Debug Monitor Exception even though I enabled it. The Cortex M33 has 4 comparators with the following functions:

Comp 0: ID Bits = 0b01011 - Cycle Counter, Instruction Address, Data Address, and Data Address With Value

Comp 1: ID Bits = 0b11010 - Instruction Address, Instruction Address Limit, Data Address, Data Address Limit, and Data Address With Value.

Comp 2: ID Bits = 0b01010 - Instruction Address, Data Address, and Data Address With Value.

Comp 3: ID Bits = 0b11110 - Instruction Address, Instruction Address Limit, Data Address, Data Address Limit, Data value, Linked Data Value, and Data Address With Value.

Cheers
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