In what situations will separate data buses ( D and S) for ARM Cortex-M4 improve performance? Also, are there any benefits of von Neuman support along with the core Harvard Architecture?
Hello,
Regarding the von Neuman architecture, it will not contribute the performance because the program is stored in the memory and CPU cannot execute until fetching it from the memory. However, the von Neuman architecture will be epoch making because program can dynamically modify the program and execute it. This means a program can produce another program and can be said as evolution of the original program.Regarding the Harvard architecture, you should drop the thinking that there are two buses but you had better get thinking that there are one instruction bus and one data bus. Unless the other bus masters do targeted to the same slave, each bus can work without disturbing.
Regarding Von Neuman architecture my point is that ARM Cortex M4 has Harvard architecture but suppose we access instructions and data from a memory above 2000_0000 , what we get is a von Neuman kind of architecture, in the sense all instructions and data appear on a single bus (SYS bus).
In this case, of course, there is no performance benefit.However, as jensbauer says, almost all MCU equips system caches for each instruction or data. For usual cases, there will be no collision on the same SRAM.
Are there any concerning points of you?
Best regards,Yasuhiko Koumoto.