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Exceptions levels in the ARMv8 architecture

Eivind

Hello

There are four exceptions levels in the ARMv8 architecture.

EL0
EL1
EL2

EL3

Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure processor states? Secure monitor?

Thanks

  • +1

    This is a picture we use in training material:

    ELs_and_Security_states.png

    EL3 is commonly used for a couple of things. 

    Secure Monitor

    ARMv8-A supports two Security states: Secure and Non-secure.  "Secure Monitor" is the name we give to code that handles switching from one Security state to another.  It's responsible for any required context switching, and ensuring that data doesn't "leak" between the worlds.

    What context needs to be switched?  Things like the general purpose registers, and possibly the FP/SIMD registers.  Also many system registers, such as the EL1 MMU related registers (TTBR0_EL1, TTBR1_EL1, TCR_EL1,...).

    Firmware

    It's common to have device specific firmware resident in EL3.  This would handle things like boot and run-time power management.  The open-source ARM Trusted Firmware is a good example.

    GitHub - ARM-software/arm-trusted-firmware: ARM Trusted Firmware