Hello,
I want to ask how interrupts queue is implemented in ARM Cortex-M processors. For example while one ISR is processing if many other interrupts will arrive, how processor will handle this interrupts queue? Also, I will appreciate links or references to official Cortex documentation.
the other kind of interrupts will be held in NVIC_ISPRn for one time.
This means the pending interrupt will be overwritten by the new interrupt.
If the new interrupt which will be put into NVIC_ISPRn has the higher priority than the interrupt which will be currently handled in ISR, the pre-emption will occur and the new interrupt ISR will be executed.
Regading the Cortex documents, please refer to the ARM information center (http://infocenter.arm.com/help/index.jsp).
Best regards,
Yasuhiko Koumoto.