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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    Trying to Freeze L1 Instruction Cache Contents on the Cortex A53 0

    • Cortex-A53
    • Cache Architecture
    • Instruction Fetch
    2586 views
    4 replies
    Latest over 3 years ago
    by rachelgomez123
  • Suggested Answer

    Porting linux on Cortex R52 FVP 0

    • Cortex-R52
    • AEMv8 FVP
    • Linux Developers
    3713 views
    2 replies
    Latest over 3 years ago
    by rachelgomez123
  • Suggested Answer

    Turn off prefetchers for cortex a72 0

    3097 views
    4 replies
    Latest over 3 years ago
    by rachelgomez123
  • Not Answered

    Looking for detailed block diagram of a single A53 core 0

    2389 views
    2 replies
    Latest over 3 years ago
    by Aswasby
  • Not Answered

    Is there possible I added interrupt vectors on the debugger for simulation? 0

    1108 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Not Answered

    Mmu | How to set different virtual address than physical 0

    • Memory Management Unit (MMU)
    2353 views
    4 replies
    Latest over 3 years ago
    by Former Member
  • Not Answered

    how to install anroid in cortex a53 0

    1026 views
    0 replies
    Started over 3 years ago
    by s nath
  • Not Answered

    Support of immediate Rorate & Shift in STM32 CortexM4 0

    • Cortex-M4
    874 views
    0 replies
    Started over 3 years ago
    by N Abid Ali Khan
  • Not Answered

    Include macro in .s file 0

    3096 views
    2 replies
    Latest over 3 years ago
    by WestfW
  • Not Answered

    Cannot flash or erase the STM32 uC anymore. 0

    1976 views
    1 reply
    Latest over 3 years ago
    by HenkvW
  • Answered

    Cortex-A32 aarch32, change from HYP mode to SVC mode fail 0

    1380 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    [Cortex-A] Permission fault due to code region mapped as read/write 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A
    2991 views
    5 replies
    Latest over 3 years ago
    by jatron
  • Not Answered

    Cortex A9 L1d cache profiling 0

    • Cortex-A9
    • performance analysis
    • Cache Controllers
    1396 views
    1 reply
    Latest over 3 years ago
    by Noemietown
  • Not Answered

    Activate ETM in Android Mobile device 0

    • mobile
    • Android
    • CoreSight ETM-A5
    • Debug and Trace
    1238 views
    0 replies
    Started over 3 years ago
    by Seongyun
  • Not Answered

    arm cortex a9 used in control edge plc 0

    769 views
    0 replies
    Started over 3 years ago
    by saneesh
  • Not Answered

    .rodata alignment 0

    • AArch64
    • GNU Assembler
    1205 views
    0 replies
    Started over 3 years ago
    by BobP
  • Suggested Answer

    In order execution 0

    1141 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Suggested Answer

    How to control the Non-Secure MPU exclusively inside the Secure world in the Cortex M33? 0

    • Memory Protection Unit (MPU)
    • TrustZone
    • Cortex-M33
    1739 views
    1 reply
    Latest over 3 years ago
    by Aurelien_Grange
  • Not Answered

    start second core from psci 0

    • AArch64
    • SMCCC
    • Cortex-A55
    • Armv8-A
    • psci
    • AArch32
    1201 views
    0 replies
    Started over 3 years ago
    by Nikita bogatov
  • Suggested Answer

    Arm MMU configuration works on (qemu) raspberry(a53) but not on virt(armv7, a53) board 0

    • Cortex-A53
    3269 views
    5 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
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