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Hi,
I'm trying to setup the physical non secure timer.
I'm in EL1 ttbr1, core0 and got there thorugh el2 so I can't modify or read SCR_EL3 but cleared HCR_EL2 so IMO, FIMO and AMO are set to 0.
I'm enabling the time like the flollwing:
asm volatile ("mrs x1, CNTFRQ_EL0"); asm volatile ("msr CNTP_TVAL_EL0, x1"); asm volatile ("mov x0, 1"); asm volatile ("msr cntp_ctl_el0, x0");
And then enabling gicc/gicd, setting the priorities and enabling int 30.
When I call a svc exception my exception table vector gets called, so I would expect the same for the timer.
But when the timer is triggered (which I'm checking with ISR_EL1 and cntp_ctl_el0) none of my functions in the exception vector is called.
DAIF is set to all 0 but ISR_EL1 does not indicate an pending irq anymore, when I set daif serror to 1. so maybe there is an exception in the timer irq call? If so, what can cause such a behavior?
greets from germany!
I've checked CNTP_CTL_EL0 and it is indeed 1 and after the timer condition is met 5(0b101). Next I checked which interrupts are pending, which are 34 (before the timeout is reached) and once the timer condition is meat 30.
I also got the qemu tracing running which says:
gic_enable_irq irq 30 enabled gic_set_irq irq 30 level 1 cpumask 0x1 target 0x1 arm_gt_tval_write gt_tval_write: timer 0 value 0x7735940 arm_gt_recalc_disabled gt recalc: timer 0 irqstate 0 timer disabled arm_gt_ctl_write gt_ctl_write: timer 0 value 0x1 arm_gt_recalc gt recalc: timer 0 irqstate 0 next tick 0x7964c07 arm_gt_recalc gt recalc: timer 0 irqstate 1 next tick 0xffffffffffffffff
At line 6 I should have gotten an irq... So the problem has to be with the exception table, right? I didn't think too much about that since my exception work just fine (I'm testing that with "svc 0xdead"), is there a way to test irqs?
Thank you so much for your replies!