Page tables using LPAE

I have a 32 bit RTOS that currently can access 32 bit physical address and I want to be able to access up to 36 bit physical address.

I made the changes but cannot get it to work even though I am still accessing only below 32 bit physical as first stage of implementation.

I went though the "Arm® Architecture Reference Manual for A-profile architecture". My understanding is once I set the TTBCR.EAE bit to enable long descriptors the MMU will automatically understand that I am using 3 levels of page tables and the VA bits used below are implied, is that correct?

Level 1 is indexes by VA virtual address bit 31:30, table with 4 entries that point to level 2 table.

Level 2 is indexed by VA bits 29:21, table with 512 entries, 4kb page , each entry points to level 3 table.

Level 3 is indexed by VA bits 20:12 , total 512 entries, 4kb page. This one has the physical address.

I created the page tables and set the lowest two bits in the long descriptor to 0x3 per spec in all 3 levels and placed the address in it..

I am using only TTBR0 that owns all the 32 bit virtual addresses and disabled TTBR1 by setting T0SZ, T1SZ to 0 per spec.

I assign the level 1 table address to TTBR0, and set TTBCR.EAE = 1 right before I turn on the MMU.

Last I put in the PC in assembly the address of the first function using virtual address so the MMU will have to translate the VA address and fetch the physical 4KB page.

However, nothing happens at that point and execution stalls.

What is it that I am still missing in my configuration?

Any help is appreciated.