Could some one explain how the cache system works when DCLS is activated on Cortex-A76AE?
As both cores serve as logically one core and provide the error check ability, all the registers needed to be reset beforehands. But what about the L1 and L2 cache? Do you reset/clear the cache as well?
Also, why does the DCLS feature can only be selected during boot time? What prevents it to be a runtime feature?