Hi, I'm trying to initialize the GICv2 interrupt controller to manage interrupts coming in the systems.
At the moment I'm not able to receive interrupts on the CPU.
It seems to me that these interrupts are pending only in case I have Group0 enabled (GICD_CTRL.bit0) but when I have Group1 enabled (GICD_CTRL.bit1) these are not propagated.
To see interrupt pending I'm looking at register GICD_ISPENDRn.
This is the first time I'm programming GICv2 and I'm using low level code.
Can you support on this?
Do you have a sequence of programming operations to be implemented for the configuration in Non Secure mode?
At the moment I'm considering the GICv2 interrupt controller but probably I need to enable the interrupts on the A53 (Core0).
Thanks a lot for your support.
Best regards Edo.
I've tried to write out a few suggestions, hope they help.In GICv2, interrupts are either Group 0 (Secure) or Group 1(Non-secure). Which Group an INTID belongs to is controlled by GICD_IGROUPRn, which is only accessible to Secure software. At reset, all interrupts are assigned to Group 0. Group 0 interrupts will be signalled as FIQs, Group 1 as IRQs.To enable interrupts you need to:
There are also some things you need to set up on the CPU itself:
Dear Martin, thanks a lot for your help.
Now we have the interrupts coming on the CPU (A53).
We have now the interrupt routine properly working but, a problem we are analysing is related to how to exit from interrupt routine itself and continue with the execution of the application. The interrupt is clear, the EOI is issued but returning at the application the pc is not correct.
We followed the rules we used in the past for all the ARM A9, Axx and Mx CPUs, but this seems not working.
There is something different on this A53 that needs to be properly uinderstood.
Thanks a lot.