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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    How to learn ARM +1

    • Cortex-M3
    • Cortex-A
    • Cortex-A7
    • Cortex-M
    6143 views
    3 replies
    Latest over 10 years ago
    by Mohamed Saleh
  • Answered

    Question about accumulator word length in A8 core 0

    • NEON
    • Cortex-A
    • Cortex-A8
    6227 views
    3 replies
    Latest over 10 years ago
    by daith
  • Answered

    Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory? 0

    • Armv7-A
    • Cache
    • Armv8-A
    • NEON
    • Cortex-A
    • TrustZone
    17437 views
    9 replies
    Latest over 10 years ago
    by Ash Wilding Arm Employee Badge
  • Answered

    Get current active interrupt priority +1

    • Cortex-M3
    • Cortex-M
    • C
    • Cortex-M4
    11013 views
    2 replies
    Latest over 10 years ago
    by Jonathan Weber
  • Answered

    LDRT and rrx'd operand 0

    • Cortex-A
    • Cortex-A7
    3851 views
    3 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    Funny asymmetry with banked register names 0

    • Armv7-A
    • Cortex-A
    • Cortex-A7
    6781 views
    5 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    Does CCI-400 guarantees cache coherency between secure and non-secure worlds? 0

    • Cortex-A53
    • Cortex-A57
    • big.LITTLE
    • CoreLink CCI-400
    • Cache
    • Cortex-A
    5368 views
    3 replies
    Latest over 10 years ago
    by Kay
  • Not Answered

    ARM Context ID Register & Process Context Switch 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    • Cortex-A8
    17590 views
    10 replies
    Latest over 10 years ago
    by onion
  • Answered

    Reordering between multiple loads 0

    • Cache
    • Cortex-A
    • Cortex-A8
    7787 views
    7 replies
    Latest over 10 years ago
    by Hemant
  • Answered

    How can we boot linux kernel in ARM FVP w/ TrustZone? 0

    • Cortex-A9
    • Cortex-A
    • TrustZone
    • Linux
    8652 views
    4 replies
    Latest over 10 years ago
    by Yoshiharu Imamoto
  • Not Answered

    Is First-level table skippable? (VMSA) 0

    • Cortex-A17
    • AArch64
    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    • AArch32
    8026 views
    4 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel? +1

    • Processor
    • Cortex-R
    • Cortex-A
    7729 views
    2 replies
    Latest over 10 years ago
    by 42Bastian
  • Answered

    How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs) +1

    • Cortex-A9
    • Cortex-A15
    • Cache
    • Cortex-A
    • Linux
    4688 views
    1 reply
    Latest over 10 years ago
    by 박주병
  • Answered

    How to set inner of outer shareability on page table entry WITHOUT TEX remap?? 0

    • Cortex-A
    • TrustZone
    6732 views
    3 replies
    Latest over 10 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world 0

    • Cortex-A53
    • Cortex-A57
    • Cortex-A
    6671 views
    3 replies
    Latest over 10 years ago
    by Axel Heider
  • Answered

    ARM v8 Arch SCTLR bit field meaning 0

    • EL1
    • EL2
    • AArch64
    8324 views
    4 replies
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ACE-Lite Master and Slaves 0

    • AMBA
    • AXI4
    • ACE-Lite
    5129 views
    2 replies
    Latest over 10 years ago
    by Uma
  • Answered

    The madman strikes again - ADD/SUB SP 0

    • Thumb
    • Cortex-A
    • Cortex-A7
    6138 views
    9 replies
    Latest over 10 years ago
    by Juha Aaltonen
  • Answered

    ASR #32 0

    • Cortex-A
    • Cortex-A7
    9200 views
    10 replies
    Latest over 10 years ago
    by Jens Bauer
  • Answered

    SMMU initialization +1

    • Cortex-A
    • Cortex-A7
    8479 views
    2 replies
    Latest over 10 years ago
    by Dav
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
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  • Cortex-A9
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  • Cortex-M0
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  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
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