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Can one ARM core debug another one in an MP/bigLITTE system?

Axel Heider

Hi,

I'm wondering, if one core could debug another one on the same or another cluster in an MP/BigLitte system ?

  • start/stop execution
  • read/write core registers
  • modify watch/breakapoints
  • full CP15 access

The use case would be a kernel debugger and the debug app running on a core, and the app to be debugged running on another core/cluster (or group of cores) exclusively reserved for debugging this app.

Does the CP14 debug interface support such a scenario?

Can a core use the functions that an external JTAG device uses?

Axel

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  • 0 Arm Employee Badge in reply to Axel Heider

    Hi Axel,

    In theory, the answer is yes: if the system designers exposed the memory-mapped view of at least a CTI which connects to the core, and the memory-mapped external debug interface for the core, in order that other cores could access it, then it's possible to do so. With the CTI you can set a trigger to halt the core, and then access the EDITR and DCC registers to move instructions and data through the core -- from another core.

    It isn't something that is baked into every ARM core, it is a function of the SoC design so you'll have to go look up some documentation on whether the debug logic and the rest of the CoreSight subsystem (for the CTIs) is exposed in the system memory map and accessible.

    Ta,

    Matt

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  • 0 Arm Employee Badge in reply to Axel Heider

    Hi Axel,

    In theory, the answer is yes: if the system designers exposed the memory-mapped view of at least a CTI which connects to the core, and the memory-mapped external debug interface for the core, in order that other cores could access it, then it's possible to do so. With the CTI you can set a trigger to halt the core, and then access the EDITR and DCC registers to move instructions and data through the core -- from another core.

    It isn't something that is baked into every ARM core, it is a function of the SoC design so you'll have to go look up some documentation on whether the debug logic and the rest of the CoreSight subsystem (for the CTIs) is exposed in the system memory map and accessible.

    Ta,

    Matt

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