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Cache maintanance operation to PoC

Luke

Hi experts,

I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller).

I'm refererring to the following operations:

- DCIMVAC, invalidate data cache by MVA to POC      (mcr  p15, 0, r0, c7, c6, 1)

- DCCMVAC, clean data cache by MVA to POC           (mcr  p15, 0, r0, c7, c10, 1)

- DCCIMVAC, clean and inv data cache by MVA to POC  (mcr  p15, 0, r0, c7, c14, 1)

As far as I know, on Cortex-A9, PoC is main external system memory (RAM) and PoU is L2 cache.

So my questions/doubts are:

1) Do these operations really clean/invalidate also L2? I'm pretty sure that PL310 needs to be cleaned/invalidate by separete instrunctions. So I think that the definition "to PoC" is quite misleading.

2) What happens if L2 (PL310) is disabled?

3) On other processors where L2 cache is "on-core" (for example Cortex-A8 and Cortex-A9) do these operations have different behavior?

Could anyone please shed some light

Thanks in advance

Regards

Luke

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