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Why does ARM Branch with Link (BL) instruction considers prefetch?

Robert

Hi,

When I read the words below dot line, I don't understand why "R14 is adjusted

to allow for the prefetch"

Could you explain it to me?

Thanks,

.......

Branch with Link (BL) writes the old PC into the link register (R14) of the

current bank. The PC value written into R14 is adjusted to allow for the

prefetch, and contains the address of the instruction following the branch

and link instruction. Note that the CPSR is not saved with the PC and

R14[1:0] are always cleared.

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  • +1 Arm Employee Badge

    The PC doesn't point at the currently executing instruction, but either 8 bytes further on (ARM) or four bytes further on (Thumb). Historically this was because the PC pointed at the instruction being fetched rather than the instruction being executed, and with a three stage pipeline that gave either +8 or +4. Although not all pipelines are the same length, the offsets are fixed for compatibility. 

    The LR is the address of the instruction we actually want to return to.  Hence, when executing a BL/BLX the PC value needs to adjusted to form the return address.

Reply
  • +1 Arm Employee Badge

    The PC doesn't point at the currently executing instruction, but either 8 bytes further on (ARM) or four bytes further on (Thumb). Historically this was because the PC pointed at the instruction being fetched rather than the instruction being executed, and with a three stage pipeline that gave either +8 or +4. Although not all pipelines are the same length, the offsets are fixed for compatibility. 

    The LR is the address of the instruction we actually want to return to.  Hence, when executing a BL/BLX the PC value needs to adjusted to form the return address.

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