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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    about tail chaning of Cortex-M0 0

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    6629 views
    4 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    AMBA +2

    • APB
    • AMBA
    • AXI
    • AHB
    5106 views
    1 reply
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    I am looking for ECC insertion method (any instruction) on any address with ARM Cortex M4. +1

    5239 views
    5 replies
    Latest over 9 years ago
    by Anuj
  • Answered

    ARM Cortex A9 second execution unit 0

    • Cortex-A9
    • Cortex-A
    9019 views
    6 replies
    Latest over 9 years ago
    by Chris Shore
  • Answered

    How to use generic timer/counter +1

    • Cortex-A57
    • Armv8-A
    • Cortex-A
    7135 views
    2 replies
    Latest over 9 years ago
    by Michael
  • Answered

    Please, request for Cortex-A53 processor..How can I buy it? +1

    • Cortex-A53
    • Cortex-A
    8541 views
    4 replies
    Latest over 9 years ago
    by Song Bin 宋斌 Arm Employee Badge
  • Not Answered

    implementing a hardware on nexys 4 ( corterx-m0) 0

    • Cortex-M0
    • Cortex-M
    2658 views
    1 reply
    Latest over 9 years ago
    by Carl Williamson Arm Employee Badge
  • Answered

    Synchronization primitives, do I need CLREX? 0

    • Armv7-M
    • Cortex-M3
    • Cortex-M
    10593 views
    6 replies
    Latest over 9 years ago
    by daith
  • Answered

    SGIs in AMP Configuration with Non-SMP Linux /RTOS +1

    • Generic Interrupt Controller
    • Cortex-A
    • Cortex-A7
    • Linux
    6354 views
    1 reply
    Latest over 9 years ago
    by semp
  • Not Answered

    About AHB5 protection control signals 0

    • AMBA 5
    • AHB
    5861 views
    4 replies
    Latest over 9 years ago
    by Santosh Matagar
  • Answered

    ReadClean transaction (ACE protocol) 0

    • ACE
    5635 views
    1 reply
    Latest over 9 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not? +1

    • AMBA
    • AHB
    6778 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)? +1

    • Cortex-M7
    • Cache
    • Cortex-M
    4473 views
    4 replies
    Latest over 9 years ago
    by amanda_s
  • Answered

    AXI3 & AXI4 wrap burst length 0

    • AXI3
    • AXI4
    17152 views
    5 replies
    Latest over 9 years ago
    by Utkarsh Jain
  • Answered

    Embedded assembly function problem 0

    • Cortex-A9
    • NEON
    • Cortex-A
    5396 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Not Answered

    What does PMCEID0_EL0 determine for the the PMU? Performance monitor config 0

    • Cortex-A57
    • Cortex-A
    4843 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    ARMv7 architecture +1

    • Armv7-A
    5152 views
    2 replies
    Latest over 9 years ago
    by Myron Plichota
  • Answered

    Spin-lock implementation for Aarch64 -- how to enforce acquire semantics? 0

    • Armv7-A
    • AArch64
    • GNU
    18333 views
    2 replies
    Latest over 9 years ago
    by Olivier Delande
  • Answered

    Need to invalidate L1 cache after DMA on Cortex A9 +1

    • Cortex-A9
    • Cache
    • Cortex-A
    8650 views
    3 replies
    Latest over 9 years ago
    by Rohan
  • Answered

    Verilog bus functional models for AHB master simulation 0

    • AMBA
    • AHB Protocol
    • CMSDK
    • Cortex-M
    11052 views
    5 replies
    Latest over 9 years ago
    by serg
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
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  • AXI
  • Cache
  • Cortex-A
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  • Interrupt
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