In the appnote "ARM Cortex-M Programming Guide to Memory Barrier Instructions" there is a section that describes the use of memory barriers in the Cortex-M processors on a case-by-case basis.
Are those cases relevant for the Cortex M7 - especially the cases which describes the interrupt enabling/disabling?
Hi,
I think the document says the affection of a store delays by a few instructions because of its pipelining.
Therefore, the document also is applicable to Cortex-M7 because it equips the pipeline.
Best regards,
Yasuhiko Koumoto.