i want to design a bridge between APB and AHB in verilog
my design consists of :
1. control clock unit (ccu) // using APB
2. my DUT contains registers module & functional module // using AHB
3. tow memories (source memory and detestation memory)
so i need to use a APB to AHB Bridge
Hi fatima,
Usually the APB protocol is a slave to the main system bus master, AHB or AXI, with a bridge to convert the more complex system bus transfers to the much simpler APB protocol.
Doing the opposite, driving a complex bus from a simpler one, means you will have to implement a very basic APB controlled AHB master which only performs single transfers, with virtually all AHB control signals tied off to static values (because there are no APB equivalent sources).
Firstly you will need to have at least APB3 so that you can add wait states to the APB transfer while attempting to read data from the AHB.
If you are implementing APB4 that also adds the possibility of performing different width write accesses to the AHB, and having a bit more control over the "protection" signal HPROT.
As an APB transfer occurs in 2 phases described in the APB protocol, the "setup" phase and the "access" phase, this could allow you to drive the AHB address and data phases of a transfer.
At the end of a "setup" phase with PSEL asserted to your bridge, you would register PADDR, PWRITE, PWDATA (and PSTRB and PPROT if APB4) on the PCLK rising edge. You can then start an AHB access, with HTRANS=NONSEQ, HADDR=PADDR, HWRITE=PWRITE, HSIZE=3'b010 (or a width calculated from the PSTRB value if APB4 and a write access), HBURST=3'b000 (SINGLE), HPROT=4'b0001 (to signal an unprivileged data access), or if APB4, 2'b00 + PPROT[0] + inverted PPROT[2], HMASTLOCK=1'b0, while driving PREADY=1'b0 back to the APB master to stall the APB "access" phase.
One cycle later drive HTRANS=IDLE and start the NONSEQ data phase transfer with PREADY=HREADY, and PSLVERR=HRESP, HWDATA = the registered PWDATA value for a write access, or combinatorially driving PRDATA=HRDATA for a read access.
If you didn't want to use the HRDATA, HREADY and HRESP returns combinatorially you could register them while adding a second PREADY=0 cycle, that way increasing the bridge access latency, but removing any potential timing issues.
I have not tested the above, but it's how I would start designing this sort of bridge if I needed one. Hope it helps you get started.
JD