In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline
given on page number C4-197 transaction permitted :
Start State - ShareClean
RRESP[3] - 0, RRESP[2] - 0
End State - Invalid or UniqueClean
Could anyone please explain with an example?
It is worth noting that these are 'Other permitted' as opposed to 'Expected' state transitions. This means that the scenarios that create these transitions may not be logical or sensible, but they will not break coherency.
In this specific case, we have a master that is storing a line in a SharedClean state, even though this line is apparently in an area of non-shareable memory (as implied by it doing a ReadNoSnoop to it). This is the point at which the line state might not be logical or sensible
The RRESP[3:2] for a ReadNoSnoop must be 2'b00, which is the interconnect telling the processor that the line is not Dirty and that it is not Shared no one else has a copy of the line (as the transaction is to non-shareable memory).
The final state of the line can then be Unique and Clean - giving us the first end state - UniqueClean. Since the line did not start in a Dirty state, and the interconnect did not pass the Dirty responsibility with the end of the transaction, we can also downgrade it to Invalid when the ReadNoSnoop completes, as there is no risk of data being lost. In contrast, if the line started as Dirty, then we cannot perform a downgrade to Invalid as otherwise data that could potentially be different from memory would be lost.