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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    Direct injection of SPIs 0

    • GICv3/v4
    • GIC Hypervisor Direct Injection
    697 views
    4 replies
    Latest 2 months ago
    by yifanfeng
  • Answered

    In CHI WriteNoSnp transaction, why DBID is required in COMP response from completer? 0

    • CHI
    408 views
    1 reply
    Latest 2 months ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Can I (and how to properly) share DTCM with DMA in Cortex-M7 0

    • Cortex-M7
    252 views
    0 replies
    Started 2 months ago
    by Yujian Zhang
  • Not Answered

    ARM Cortex R52+ Data Cache Misses mis-calculation 0

    • Cortex-R52
    • Cache
    • Cache Architecture
    192 views
    0 replies
    Started 2 months ago
    by Alessandro Comodi
  • Answered

    C2C Snoop address mapping between CHI 0

    • snoop
    • CHI
    • C2C
    364 views
    1 reply
    Latest 2 months ago
    by Ben Hicks Arm Employee Badge
  • Answered

    C2C SNP Address width diff from CHI 0

    • CHI
    • C2C
    1226 views
    7 replies
    Latest 2 months ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Question about the performance overhead introduced by the MTE mechanism 0

    • performance
    • Cortex-A
    • MTE
    • SPEC2017
    349 views
    0 replies
    Started 2 months ago
    by Peng Mingfan
  • Not Answered

    Where can I find the description of hwcpipe_counter? 0

    202 views
    0 replies
    Started 2 months ago
    by Qing Chen
  • Not Answered

    ARMv8 halt address after reset with EDECR.RC set 0

    • Armv8-R
    218 views
    0 replies
    Started 2 months ago
    by Lee Leon
  • Answered

    How to automatically reset CR52 with warm reset request 0

    • Cortex-R52
    • Armv8-R
    474 views
    1 reply
    Latest 3 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    How To Access SCTLR_EL1 of Non Secure World From EL3 0

    • EL3
    • Trusted Firmware-A
    • fvp
    910 views
    4 replies
    Latest 3 months ago
    by Dev Gandhi
  • Suggested Answer

    Handshake signal behavior in CHI spec 0

    • UCIe
    • CHI
    • C2C
    486 views
    1 reply
    Latest 3 months ago
    by Simone Secchi Arm Employee Badge
  • Not Answered

    Exclusive store op hang 0

    241 views
    0 replies
    Started 3 months ago
    by Djole Prolece
  • Not Answered

    Arm Cortex M4 Exception Exit Being interrupted 0

    • Cortex-M4
    256 views
    0 replies
    Started 3 months ago
    by Satyajit Patil
  • Answered

    Stalls in float point calcultions 0

    • NEON
    • pipeline
    • SVE2
    • SVE
    • Floating Point
    748 views
    3 replies
    Latest 3 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Cortex A53 Cycle Counting, Single-Step 0

    • Armv8-A
    • Performance Monitor Unit (PMU)
    • Debug Access Port (DAP)
    790 views
    2 replies
    Latest 3 months ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Some instruction variants' encodings in `Instructions.json` missing constant bits. 0

    466 views
    1 reply
    Latest 3 months ago
    by Mohamed Maaliki
  • Suggested Answer

    Can Cross Trigger Configure Multiple Cores to Halt Simultaneously in Self-Hosted Debug? 0

    • Armv8-A
    489 views
    1 reply
    Latest 3 months ago
    by Stephen Theobald Arm Employee Badge
  • Not Answered

    GIC-700 SPI routing in multichip system 0

    • Multichip
    • GICv3/v4
    • Interrupt
    • spi
    245 views
    0 replies
    Started 3 months ago
    by RH Kim
  • Not Answered

    Unable to Read/Write Non-Secure EL1 System Registers (e.g., SCTLR_EL1) from EL3 on FVP with OP-TEE and TF-A 0

    • Arm Trusted Firmware
    • Interrupt Handling
    • EL3
    • Armv8-A
    • Trusted Firmware-A
    • TrustZone
    • fvp
    • Linux
    369 views
    0 replies
    Started 3 months ago
    by Dev Gandhi
<>
Topics being discussed in this forum
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