I am reading GIC-700 TRM, and seems that it can directly inject SGIs/LPIs into virtual machine without be trapped into Hypervisor. Unfortunately, SPIs direct injection is not supported. I am wondering if there is some special considerations to not suppport SPI direct injection? To me, if there is options to configure every single SPI to trap or not into Hypervisor, the performance will be better.
yifanfeng said:I am reading GIC-700 TRM, and seems that it can directly inject SGIs/LPIs into virtual machine without be trapped into Hypervisor.
That's correct, GICv4.1 (which is what GIC-700 implements) only supports direct-injection of SGI/LPIs.
yifanfeng said:I am wondering if there is some special considerations to not suppport SPI direct injection?
Direct-injection of SPIs, and also PPIs, comes in the recently announced GICv5 spec.
https://developer.arm.com/Architectures/Generic%20Interrupt%20Controller
Many thanks for the replying, Martin. BTW, what's ARM's plan to implement the GICv5 (GIC-800 for instance)? And for Cortex-A720 core, is it possible that we wrap GIC-700 somehow to get the SPIs directly injected to virtual machine?
yifanfeng said:And for Cortex-A720 core, is it possible that we wrap GIC-700 somehow to get the SPIs directly injected to virtual machine?
Not easily.
If the interrupt sources have edge semantics, you could have a system component to convert the wires to MSIs. Those MSIs would go to the ITS becoming LPIs instead of SPIs, which lets you use direct-injection.
If the interrupts have level semantics it is harder, because the GICv4 ITS doesn't cope with levels (that's one of the things that come with GICv5).
Many thanks, Martin.