Arm Cortex M4 Exception Exit Being interrupted

I am using NXPS32M244 platform which has Arm cortex M4. I am developing autosar OS. 

I have a common interrupt handler for all irq and systick exception. I understand that an interrupt or exception has to be serviced in the handler mode only. So, on event of interrupt, I am storing context (all regs including stack frame) in global context (an entity specific space reserved to store context of running entity) and manually loading context registers of peripheral ISR manually. 

The context loading api is guarded with "CPSID i" and "CPSIE i" instruction as shown below - r0 is the address of global context and at #24, the ISR entry function address is stored which is being loaded in r5. And, after enabling global interrupts execution should jump to entry function of ISR. 

Note - OS is taking care of storing and loading context which has to be done in controlled and high priority environment, so I have disabled the global interrupt and enabling it just before jumping to entry function.

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LDR r5, [r0, #24]
CPSIE I
BX r5
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

So, the question is, if context loading is running for irq with priority 2 and meanwhile systick exception occures with pririty zero, then will "BX r5" be interrupted?  Right after clearing PRIMASK (CPSIE i).

Also, I have a few more instances like this - While terminating an ISR routine. Once ISR execution completes, it jumps to an OS ISR_termination function, which load the context of preempted entity in global context and calls an assembly routine, this complete termination process is also guarded with "CPSID i" and "CPSIE i". One of the instances to jump to thread mode is shown below - 

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LDR LR,=0xFFFFFFFD
CPSIE I
BX LR
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
So, same as previous, will this BX LR can also be interrupted. As scene is a bit different here, the core will load the stack frame into registers and will do integrity check also. So, can this be interrupted? Also, how many cycles does the core takes for BX LR operation (including tasks - integrity checks, stack unwinding, IPSR update). Can this whole operation be interrupted once begin? 

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