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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Not Answered

    Armv7-a TrustZone cps instruction Question 0

    476 views
    5 replies
    Latest 1 month ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Snoops for access to inner/outer shareable domain 0

    • corelink cmn-600
    • DSU
    263 views
    1 reply
    Latest 1 month ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Two different OS on different cores in same cluster with no EL2 enabled 0

    • EL2
    481 views
    4 replies
    Latest 1 month ago
    by yifanfeng
  • Not Answered

    Why ARM A720AE treats non-shareable as non-cacheable? 0

    114 views
    0 replies
    Started 1 month ago
    by yifanfeng
  • Answered

    Cortex-M0 initialization | Minimum requirements 0

    • Cortex-M0
    378 views
    2 replies
    Latest 1 month ago
    by Igor
  • Suggested Answer

    Illegal Instruction Exception 0

    596 views
    4 replies
    Latest 1 month ago
    by Peter Harris Arm Employee Badge
  • Not Answered

    SMP kernel over multi-cluster ARMv9 cores 0

    • GICv3/v4
    • DSU
    131 views
    0 replies
    Started 1 month ago
    by yifanfeng
  • Not Answered

    Inquiry: Does ARM Errata ID 838869 apply to Cortex-M7? +1

    • Cortex-M7
    682 views
    1 reply
    Latest 1 month ago
    by Daniel Ka
  • Not Answered

    The behaviour of writenosnp and readnosnp that require request order in CHI 0

    185 views
    0 replies
    Started 1 month ago
    by York Tsang
  • Suggested Answer

    Cortex M3 sc300 DHCSR Regist 0

    495 views
    1 reply
    Latest 1 month ago
    by Mahmood Yakub Arm Employee Badge
  • Not Answered

    MPAM support in Linux mainline 0

    210 views
    0 replies
    Started 1 month ago
    by yifanfeng
  • Answered

    Unexpected result from svqdmulh_s32 with negative input values +2

    • intrinsics
    • NEON
    • Cortex-A
    • SVE2
    417 views
    1 reply
    Latest 1 month ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    SVE/SVE2 issue on Cortex-A320 example 0

    • SVE
    834 views
    5 replies
    Latest 1 month ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    clarifications about ARCACHE bits in AXI4 0

    177 views
    0 replies
    Started 2 months ago
    by Srilakshmi beeram
  • Not Answered

    Restrict Speculative Access +1

    572 views
    3 replies
    Latest 2 months ago
    by Youq
  • Answered

    In Cortex-R5, the address of cache maintenance operations is not restricted by the MPU ? 0

    • Cortex-R
    667 views
    4 replies
    Latest 2 months ago
    by SmileSX
  • Not Answered

    Configure MPAM in Hypervisor even if virtual machine OS did not take care of MPAMx_EL1 0

    143 views
    0 replies
    Started 2 months ago
    by yifanfeng
  • Not Answered

    The CM7 CoreMark score is not ideal. 0

    168 views
    0 replies
    Started 2 months ago
    by depei zhang
  • Not Answered

    ACE - CHI protocol conversion 0

    173 views
    0 replies
    Started 2 months ago
    by Arjun Singh
  • Not Answered

    Use of smlad in arm_fir_decimate_fast_q15 function 0

    153 views
    0 replies
    Started 2 months ago
    by John Atkins
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Topics being discussed in this forum
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