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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3580 Questions
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  • Answered

    Cache and store buffer maintenance in cortex-a8! 0

    • Armv7
    • Cache coherency
    • Cortex-A
    • Cortex-A8
    8154 views
    6 replies
    Latest over 11 years ago
    by Hamed
  • Answered

    What will I get if I try to access SCR in cp15 when my core is in non secure mode. +1

    • TrustZone
    6158 views
    4 replies
    Latest over 11 years ago
    by Jay Zhao
  • Answered

    Which ARM core is best suited for DSP applications? 0

    • DSP
    • Cortex-R
    • Cortex-A
    8066 views
    5 replies
    Latest over 11 years ago
    by Dr. Paul Beckmann
  • Answered

    Code for integer division on Cortex-A8? 0

    • Cortex-A8
    16745 views
    12 replies
    Latest over 11 years ago
    by daith
  • Answered

    Question on duration of hsel in AHB +1

    • Timing
    • AMBA
    • AHB
    7416 views
    1 reply
    Latest over 11 years ago
    by Ben Hicks Arm Employee Badge
  • Answered

    Synchronisation Primitives and Exclusive Monitors 0

    4221 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Difference between thumb machine directives 0

    • Thumb
    12552 views
    3 replies
    Latest over 11 years ago
    by daith
  • Answered

    Use case of MSP and PSP in Cortex M 0

    47967 views
    1 reply
    Latest over 11 years ago
    by Chris Shore
  • Answered

    Cortex-M4 interrupt priority dynamically change while in ISR 0

    • Cortex-M4
    • Interrupt
    19907 views
    14 replies
    Latest over 11 years ago
    by Adnan Ashraf
  • Answered

    Recently i bought a new kit supporting cortex m0+ processor ! I read the complete datasheet but could not find the instruction for using GPIO !! 0

    • Cortex-M0+
    4080 views
    1 reply
    Latest over 11 years ago
    by Jens Bauer
  • Answered

    ASM instruction error 0

    • Cortex-A
    • Arm Assembly Language (ASM)
    9217 views
    5 replies
    Latest over 11 years ago
    by techguyz
  • Answered

    Is Cortex-A56 Maia or Artemis? 0

    • Armv8
    • 64-bit
    10119 views
    2 replies
    Latest over 11 years ago
    by wangyong
  • Answered

    Is the functionality of TZC400 working on ARMv8 FVP base model? +1

    • Corelink
    • Armv8
    • CoreLink TZC-400
    5231 views
    3 replies
    Latest over 11 years ago
    by SY Chiu
  • Answered

    Can a Linux kernel run as a TrustZone secure OS? +1

    • TrustZone
    • Interrupt
    16714 views
    6 replies
    Latest over 11 years ago
    by Sudeep Holla Arm Employee Badge
  • Answered

    Getting Started in Real-Time Applications 0

    • Real-Time
    5976 views
    4 replies
    Latest over 11 years ago
    by Alban Rampon
  • Answered

    Cryptography instructions sample for ARMv8 0

    • Armv8
    • Armv8-A
    5223 views
    1 reply
    Latest over 11 years ago
    by Sudeep Holla Arm Employee Badge
  • Answered

    ARM Cortex A8 - if IRQ interrupts are disabled in CPSR register While the processor is executing, system results in data abort. What might be the reason to trigger data abort +1

    • CPSR
    • Cortex-A
    • Cortex-A8
    • Processors
    • Interrupt
    5640 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    What happens if an interrupt occurs as it is already disabled +1

    • Armv7
    • Cortex-A
    • Cortex-A8
    • Interrupt
    10943 views
    2 replies
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    Few beginner questions - from AVR to ARM 0

    • Raspberry Pi
    • Embedded
    34293 views
    28 replies
    Latest over 11 years ago
    by kamran
  • Answered

    Cortex-A7 4 Cores Boot +1

    • Cortex-A
    • Cortex-A7
    6514 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
<>
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