Hi,
I am looking on some info on prefetch (of instruction) in cortex-r.
I have a very inefficient (power wise) memory which usually is not access, even with branch predictor I will have many unneeded accesses.
In some older ARM architecture there was a known note it can not cross 1-KB boundary. Is there any known (published) statement for cortex-R?
Thanks,
Yaniv
Which Cortex-R processor(s)?
In ARMv7-R the processor can speculatively fetch an instruction from any address marked as executable (*). Whether a given processor will do so, and under what circumstances, is a micro-architectural question.
If you could avoid placing any instructions in the slow memory you could then mark it as XN (execute never). This would prevent speculative instruction fetches.
(* See section B5.2.1 of the ARMv7-A/R Architecture Reference Manual rev C.c)
Hi solyan-san,
there are the following descriptions in the Cortex-R Technical Reference Manuals.
"Cortex-R5 Technical Reference Manual Revision: r1p2"
9.3.1 Restrictions on AXI transfers No transaction ever crosses a 32-byte boundary in memory.
9.7.7 AXI peripheral port transfers No transaction ever crosses a 8-byte boundary in memory.
9.7.8 AHB peripheral port transfers No transaction ever crosses a 8-byte boundary in memory.
"Cortex-R4 and Cortex-R4F Technical Reference Manual Revision: r1p4"
Regarding the TCMs, there are no such descriptions. I guess that transaction for the TCMs have no such boundary restrictions.
Best regards,Yasuhiko Koumoto.