As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ
My question is specific to the case when it is only the cacheability that is different across aliases. E.g., consider a physical page @0x80000000 mapped @0xE0000000 and @0xF0000000 with
1) mapping @0xE0000000 is normal memory, inner (L1) + outer (L2) cacheable
2) mapping @0xF0000000 is normal memory, inner (L1) cacheable only
Now, in the system , if there are 2 execution threads (may even be across public, secure modes) using the above virtual addresses to access, share the same physical region but taking care of L2 clean/inv before using 0xF0000000 to access the same region, do you see this falls into UNPREDICTABLE operation due to mismatched attributes?
Thanks.