Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

Hello,

Consider following scenario:

1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
2. Now, the s/w writes to the first word in the page. Let's assume valid line was already present in L1 and is now updated after this write. Thus the concerned line becomes dirty in L1.
3. Over the period of time / load, this line is up for eviction

At this time, my question is, since original attributes for this line were not "outer cacheable", will the line still may be allocated into L2, or will directly be written to L3, always?

If, L2 is skipped in the above scenario, does that mean the line type information is stored in L1 ? That is, something like AWUSER[4:1] is stored somewhere for each line?

What if L2 is in exclusive cache mode?

Thanks.