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I find the description below from MMU-500 TRM.
Address width
The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address
bus is 48 bits.
But I know that the AXI address width of Cortex-A53/57 is 44 bits.
So If Cortex-A53/57 and MMU500 are connected with the same CCI-400 interconnect, will CCI-400 ensure the matching of address width, or will MMU500 only connect 44 bits output address with CCI-400?
And I find that the address width of Cortex-A7/15 and MMU-400 is 40 bits, I am confused about MMU-500.
Would you please kindly explain this? Thanks.
It's to support stage 1 translation.
The virtual address space in AArch64 is 48 bits (0x0 to 0x0000,FFFF,FFFF,FFFF). For EL1/0 there is another 48-bit range at the top of the 64-bit range (0xFFFF,0000,0000,0000 to 0xFFFF,FFFF,FFFF,FFFF).
The figure you quoted (44 bits) is the size of the supported physical address width.
When configured to perform stage 1 translation, the SMMU needs to support these address ranges as inputs.
Thanks.
According to your description I am clear about why MMU-500 has 48-bits address. But the physical address width of Cortex-A53/A57 and CCI-400 is 44 bits, and the physical address width of MMU-500 is 48 bits. So when MMU-500 is connected with CCI-400, does MMU-500 only use 44 bits?
Something I should have added to my earlier post... ARM8-A allows for up to 48 bits of physical address. While the Cortex-A57/A53 don't support that many, other implementations might.
Looking the CCI-400 TRM, it supports up to 40-bits of physical address:
ARM CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: 3.4. Address map
This doesn't change the fact that the MMU-500 would need to support 49-bit addresses as inputs, if you wanted to be able to do stage 1 translations. But it would give a practical limit on the size of physical address you could translate to.
Thanks a lot. I also find that the address width of MMU500 is configurable from the description below.
SMMU_IDR2:
UBS, bits[11:8] Upstream Bus Size. The encoding of this field is:
0b0000 32-bit upstream bus size.
0b0001 36-bit upstream bus size.
0b0010 40-bit upstream bus size.
0b0011 42-bit upstream bus size.
0b0100 44-bit upstream bus size.
0b0101 49-bit upstream bus size.
OAS, bits[7:4] Output Address Size. This specifies the maximum number of PA bits that an SMMU implementation supports:
0b0000 32-bit.
0b0001 36-bit.
0b0010 40-bit.
0b0011 42-bit.
0b0100 44-bit.
0b0101 48-bit.
IAS, bits[3:0] IPA Address Size. This specifies the maximum number of IPA bits that an SMMU implementation supports: