I find the description below from MMU-500 TRM.
Address width
The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address
bus is 48 bits.
But I know that the AXI address width of Cortex-A53/57 is 44 bits.
So If Cortex-A53/57 and MMU500 are connected with the same CCI-400 interconnect, will CCI-400 ensure the matching of address width, or will MMU500 only connect 44 bits output address with CCI-400?
And I find that the address width of Cortex-A7/15 and MMU-400 is 40 bits, I am confused about MMU-500.
Would you please kindly explain this? Thanks.
Thanks a lot. I also find that the address width of MMU500 is configurable from the description below.
SMMU_IDR2:
UBS, bits[11:8] Upstream Bus Size. The encoding of this field is:
0b0000 32-bit upstream bus size.
0b0001 36-bit upstream bus size.
0b0010 40-bit upstream bus size.
0b0011 42-bit upstream bus size.
0b0100 44-bit upstream bus size.
0b0101 49-bit upstream bus size.
OAS, bits[7:4] Output Address Size. This specifies the maximum number of PA bits that an SMMU implementation supports:
0b0000 32-bit.
0b0001 36-bit.
0b0010 40-bit.
0b0011 42-bit.
0b0100 44-bit.
0b0101 48-bit.
IAS, bits[3:0] IPA Address Size. This specifies the maximum number of IPA bits that an SMMU implementation supports: