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Cortex-R prefetch behavior? Does it cross page boundary?

Yaniv

Hi,

I am looking on some info on prefetch (of instruction) in cortex-r.

I have a very inefficient (power wise) memory which usually is not access, even with branch predictor I will have many unneeded accesses.

In some older ARM architecture there was a known note it can not cross 1-KB boundary. Is there any known (published) statement for cortex-R?

Thanks,

Yaniv

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  • +1

    Hi solyan-san,

    there are the following descriptions in the Cortex-R Technical Reference Manuals.

    "Cortex-R5 Technical Reference Manual Revision: r1p2"

    9.3.1 Restrictions on AXI transfers
      No transaction ever crosses a 32-byte boundary in memory.

    9.7.7 AXI peripheral port transfers
      No transaction ever crosses a 8-byte boundary in memory.

    9.7.8 AHB peripheral port transfers
      No transaction ever crosses a 8-byte boundary in memory.

    "Cortex-R4 and Cortex-R4F Technical Reference Manual Revision: r1p4"

    9.3.1 Restrictions on AXI transfers
      No transaction ever crosses a 32-byte boundary in memory.

    Regarding the TCMs, there are no such descriptions. I guess that transaction for the TCMs have no such boundary restrictions.

    Best regards,
    Yasuhiko Koumoto.

Reply
  • +1

    Hi solyan-san,

    there are the following descriptions in the Cortex-R Technical Reference Manuals.

    "Cortex-R5 Technical Reference Manual Revision: r1p2"

    9.3.1 Restrictions on AXI transfers
      No transaction ever crosses a 32-byte boundary in memory.

    9.7.7 AXI peripheral port transfers
      No transaction ever crosses a 8-byte boundary in memory.

    9.7.8 AHB peripheral port transfers
      No transaction ever crosses a 8-byte boundary in memory.

    "Cortex-R4 and Cortex-R4F Technical Reference Manual Revision: r1p4"

    9.3.1 Restrictions on AXI transfers
      No transaction ever crosses a 32-byte boundary in memory.

    Regarding the TCMs, there are no such descriptions. I guess that transaction for the TCMs have no such boundary restrictions.

    Best regards,
    Yasuhiko Koumoto.

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