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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3594 Questions
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  • Answered

    How to deice debug target exception level of watchpoint on ARMv8 architecture 0

    • EL1
    • EL2
    • AArch64
    • Armv8
    6066 views
    2 replies
    Latest over 9 years ago
    by Myoungjae Kim
  • Answered

    arm v7AR debug architecture DCC register access 0

    • Armv7-A
    • Armv7-M
    6336 views
    3 replies
    Latest over 9 years ago
    by Michael Williams Arm Employee Badge
  • Answered

    Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9? +1

    • Cortex-A9
    • Cache
    • Cortex-A
    8458 views
    4 replies
    Latest over 9 years ago
    by Matt Sealey Arm Employee Badge
  • Answered

    Exceptions levels in the ARMv8 architecture +1

    • Arm Trusted Firmware
    • Armv8
    8772 views
    1 reply
    Latest over 9 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Enabling NEON Instructions on Pixhawk 0

    • NEON
    • Cortex-M
    • Cortex-M4
    3999 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Not Answered

    coming from AVR 8-bitter,starting ARM CORTEX-M programming 0

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    • GNU
    9007 views
    5 replies
    Latest over 9 years ago
    by Tony Cook
  • Answered

    cmsis NVIC question. +1

    • Cortex-M0
    • Armv6-M
    • Cortex-M3
    • Cortex-M
    • CMSIS
    • C
    • Cortex-M4
    5044 views
    1 reply
    Latest over 9 years ago
    by Simon Craske Arm Employee Badge
  • Answered

    Bootcode geneartion from C testcase for Cortex_R4 +1

    • Cortex-R4
    6703 views
    5 replies
    Latest over 9 years ago
    by raj
  • Answered

    MIPS Calculation on ARMv7 +1

    • Armv7-A
    • Armv7-M
    • Arm9
    12761 views
    5 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Not Answered

    ARM CM4 FPU execption 0

    • Cortex-M
    • Cortex-M4
    3492 views
    3 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    Cortex-M interrupts queue +1

    • Cortex-M
    5212 views
    1 reply
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    In aarch32 state, what is the mechanism to switch to aarch64 in software? 0

    • EL1
    • AArch64
    • AArch32
    11758 views
    5 replies
    Latest over 9 years ago
    by cray
  • Answered

    [ELF/Thumb] Is it possible to create library procedures in Thumb-mode only ? 0

    • Thumb2
    • Linux
    7052 views
    3 replies
    Latest over 9 years ago
    by Myy
  • Answered

    Read/Write from register +1

    • Cortex-M0
    • Cortex-M
    • C
    5358 views
    3 replies
    Latest over 9 years ago
    by G. Goodwin L. Pitos
  • Answered

    Data Abort Exception in A53 +1

    • Cortex-A53
    • AXI
    • Memory Management Unit (MMU)
    • Cortex-A
    7482 views
    3 replies
    Latest over 9 years ago
    by Kelvin Arm Employee Badge
  • Answered

    Bit-banding in SRAM region (Cortex-M4) +1

    • Cortex-M
    • C
    • Cortex-M4
    8932 views
    5 replies
    Latest over 9 years ago
    by Matic
  • Answered

    What is the difference between instruction prefetch and instruction pipelining in arm7tdmi? +1

    • Arm7
    12300 views
    6 replies
    Latest over 9 years ago
    by Yasuhiko Koumoto
  • Answered

    can anyone tell me the difference between pipelined bus and depipelined bus?and i have uploaded two screen shot of both so what does that arrow from mclk to a[31:0] indicates? 0

    • Arm7
    14329 views
    9 replies
    Latest over 9 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Assembly programming - yes, no, when, how to start, ... ?? 0

    • Raspberry Pi
    • Cortex-M
    • C
    10517 views
    8 replies
    Latest over 9 years ago
    by Thibaut ZEISSLOFF
  • Answered

    How to get absolute value of a 32-bit signed integer as fast as possible? +1

    • 32-bit
    • Cortex-M
    • C
    • Cortex-M4
    42066 views
    12 replies
    Latest over 9 years ago
    by Thibaut ZEISSLOFF
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