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Cache Coherence

Rohan

Hi ,

   I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid.

   1. Bring Core 1 out of reset.

   2. Bring Core 2 out of reset.

   3. Invalidate Core 2 data cache. Enable data cache.Set SMP mode with ACTLR.SMP. Enable MMU.

   4. Enable SCU . Invalidate TAG rams. Invalidate L2 cache. Enable L2 cache.

   5. Invalidate Core 1 data cache. Enable data cache. Set SMP mode with ACTLR.SMP. Enable MMU.

   6. Core1 Initiate  cache-able Write  access to location 10 with Data 'h5. (Data stored in L1 cache)

   7. Core2 Initiate  cache -able Read access to location 10 .

   8. Should the data  expected  by Core 2 is 'h5 or the memory data ?.

Regards,

Rohan

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