Hi, I am using arm cortex m4
I have following code:
main() { fun1(); } void fun1() { uint8_t frame[256]; fun2(frame); } void fun2(uint8_t *frame) { uint32_t temp; temp = *(uint32_t *)(frame + 1); printf("%d", temp); }
Will temp variable prints 32 bit value correctly?
I mean to ask, if address generated (frame + 1) is odd and not on 4 byte boundary then will it be able to load 32 bit value correctly on cortex m4?
I have read following ARM Information Center , it states that:
"The ARMv6 architecture introduced the first hardware support for unaligned accesses. ARM11 and Cortex-A/R processors can deal with unaligned accesses in hardware, removing the need for software routines"
But what about cortex m4?
Is it same?
I think that arm v4T does not support this alignment and in such case we need to explicitly copy the data byte by byte?
Am I correct?
Please elaborate.
Thanks for reading mu question.
Also, thanks in advance for your answers.
Hello,
Cortex-M4 supports an unaligned access by default.
If CCR.UNALIGN_TRP is set to '1', an unaligned access will cause exception.
I verified this by my Cortex-M4 board (FRDM-K64F).
Best regards,
Yasuhiko Koumoto.
Thanks for Checking....
For e.g. LPC2148 does not supports this....
Please confirm.
Hello,No, LPC2148 does not supports an unaligned accesses.Although I cannot catch you intention, isn't the following code inappropriate?
void fun2(uint8_t *frame) { uint32_t temp; temp = (*(uint32_t *)(frame)>>8)|(*(uint32_t *)(frame+4)<<24); printf("%d", temp); }
Best regards,Yasuhiko Koumoto.
Hi hemantraj2007,
Hardware support for unaligned accesses was first introduced in ARMv6 as mentioned in the article that you cited (How does the ARM Compiler support unaligned accesses?). Cortex-M4(F) is based on ARMv7-M and supports unaligned accesses (as confirmed by Yasuhiko). ARMv4/v4T is an older architecture and devices like LPC2148 which are based on ARM7TDMI-S don't support unaligned accesses.
Copying the 32-bit data byte by byte will need 4 memory read cycles. Yasuhiko's code reads whole 32-bit word from the two memory locations straddled by the misaligned data. The broken data is then reassembled using shifts and OR operations. The number of memory read cycles in this case is only 2.
Regards,
Goodwin
Thanks a lot !!