Cortex A9 CPU self-tests

Hi!

I am currently working in a project with a Freescale i.MX6 (Cortex A9) board. The system has to be certified against the ISO 13849 standard and my job is to implement software diagnostics in accordance to ISO 13849.

Now my problem is that ISO 13849 states the following: “Processing unit: self-test by software.” Which doesn’t really say much at all, but I have been told that I can consult IEC 61508 for more details regarding this requirement.

According to IEC 61508 the CPU self-test can be done in the following way:

“Self-test by software: limited number of patterns (one-channel)

Aim: To detect, as early as possible, failures in the processing unit.

Description: The hardware is built using standard techniques which do not take any special safety requirements into account.

The failure detection is realised entirely by additional software functions which perform self-tests using at least two complementary data patterns 

(for example 55hex and AAhex).” 

OR by doing:

“Self-test by software: walking bit (one-channel)

Aim: To detect, as early as possible, failures in the physical storage (for example registers) and instruction decoder of the processing unit.

Description: The failure detection is realised entirely by additional software functions which

perform self-tests using a data pattern (for example walking-bit pattern) which tests the physical storage (data and address registers) and the instruction decoder.

However, the diagnostic coverage is only 90 %.”

The way I interpret things is that I can write walking-bit pattern or complementary data patterns to the registers of the CPU, am I right?

So my question is, which registers of the Cortex A9 CPU do I need to check in order to perform a CPU self-test and how is that done? Is there any software libraries out there that  I can use?

Any help is greatly appreciated.

/Daniel