Hello ,
i can see that AXI have some bits : AWID ARID BID ARID RID , those bits role is trasaction ordering , well i want to know how axi form those bits , i heard (i dont know if it is true) that a master can use those bits to find his path to the slave (though multiple interconnects) , (i heard many people talk for those bits as thread bits ), i would like too know how can i test those bits with vivado ? (any ideas ) , how does those bits affect ordering restrictions on AXI?
tnx you
Hi giannis,
Where I talked about "add extra bits to the AWID, ARID and WID" outputs, I was referring to what the interconnect logic between the AXI master and slave might add, not what the AXI master does. What those additional interconnect added ID bits might be will depend on the interconnect design, and the complexity of the system being connected together. You would hopefully see this described in the interconnect logic documentation.
For the "R5 arm unit", it will have specific ID encodings that it uses for specific operations, and you will usually find these described in the technical reference manual, but you shouldn't design any slave logic to perform specific operations based only on the IDs because firstly they could change between revisions of the AXI master design, and secondly the slave won't see those exact ID encodings because they will almost certainly be changed in some way by the interconnect logic.
So rather than worry about how to decode or interpret the ID values received by the AXI slave, just treat the ID as a tag field to link together the transfers on the AW, W and B channels, or the AR and R channels, and then just perform the transfer being requested on the other AXI address channel signals.
JD