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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3587 Questions
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  • Answered

    What will happen when cacheline is mismatch 0

    • Cache
    • Cache Management
    • Cortex-A
    • Cortex-M
    1038 views
    2 replies
    Latest 6 months ago
    by junhao.wang
  • Answered

    Does Cortex-A53 support Separate Start Address? 0

    • Cortex-A53
    859 views
    1 reply
    Latest 6 months ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
    • SMMUv3
    • Cortex-A55
    • Cache Management
    441 views
    0 replies
    Started 6 months ago
    by Adithya SM
  • Suggested Answer

    Halt-on-debug scenario, halt the system counter when halting. 0

    • Cortex-A9
    • CoreSight Debug and Trace
    • Armv8-A
    • Cortex-A
    1763 views
    5 replies
    Latest 6 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

    1621 views
    5 replies
    Latest 6 months ago
    by Jake Zhao
  • Answered

    How to generate LPI with ITS? 0

    848 views
    1 reply
    Latest 6 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    687 views
    1 reply
    Latest 6 months ago
    by steve jeong
  • Answered

    Cortex-R52+ asynchronous abort 0

    • abort
    • Cortex-R52+
    1269 views
    3 replies
    Latest 7 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

    • AMBA
    • AXI
    350 views
    0 replies
    Started 7 months ago
    by Manikanta Kopparapu
  • Not Answered

    Measured Boot Implementation with TF-A and OP-TEE on Jetson Orin Nano 0

    • secruity
    • measured boot
    • jetson orin nano
    • optee
    • jetpack
    1177 views
    0 replies
    Started 7 months ago
    by Niklas Flink
  • Answered

    How to mapping MSI (LPIs) in Linux kernel 6.12.y ? +1

    1756 views
    3 replies
    Latest 7 months ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Multi-Master APB Subsystem 0

    386 views
    0 replies
    Started 7 months ago
    by Abdelrahman Ehsan
  • Suggested Answer

    Enable exceptions for dividing by zero float for CORTEX R7 0

    • Exception Handling
    • division by zero
    • Cortex-R
    • Floating-Point Execution
    • Cortex-R7
    936 views
    1 reply
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Are Stage 1 & 2 walk repeat loops bounded? 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    2789 views
    5 replies
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    Does integrated MCU consume memory bandwidth extremely, within a (Quad-A55 + MCU) SOC ? 0

    447 views
    0 replies
    Started 7 months ago
    by duanlin
  • Answered

    Amount of data that can be sent with one CMSIS-DAP data transfer command 0

    • DAP
    • CMSIS
    • CoreSight
    2041 views
    6 replies
    Latest 7 months ago
    by Oom Sats
  • Suggested Answer

    ARMv8 Cortex-A55 How to enable cache protection behavior 0

    • AArch64
    • Cortex-A55
    • Cache
    • Armv8-A
    939 views
    1 reply
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    ARM CCA 0

    • cca
    995 views
    1 reply
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    How is cache addressing assigned on the R5? 0

    • Cortex-R5
    1283 views
    3 replies
    Latest 7 months ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    A53 NEON memory access behavior 0

    • AXI4
    • Armv8-A
    • NEON
    • a53
    645 views
    1 reply
    Latest 7 months ago
    by Dylan Barrie
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Topics being discussed in this forum
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