howdy,
application scenarios:
Quad-A55 AMP system, target core is a bare-metal system all run in Non-Secure EL1 with interrupt preemption enabled. and EOI mode is drop/deactive together.
normal situation:
The guide documents said the order of ICC_EOIR1_EL1 must be the reverse order of ICC_IAR1_EL1 interrupt acknowledge. The INTID read from ICC_IAR1_EL1 should be perserved by software. This no problem.
question situation:
After a jtag-debugger relaunch, this probably not caused any reset to GIC in my debug platform, because GIC is still servicing for other cores in AMP system.If the relaunch occured between read ICC_IAR1_EL1 and write ICC_EOIR1_EL1, there is a breakpoint for e.g. then the INTID is lost after the relaunch.This situation ICC_RPR_EL1 remains the priority of last ICC_IAR1_EL1, If do not drop down ICC_RPR_EL1 to 0xFF, then the lower priority interrupts will not able to be rised.
GICD/GICR_ICACTIVE<n> cannot drop down ICC_RPR_EL1, and foreach active-state interrupt to find INTID is complicated also not reliable.
the question:
Is there any way to drop down ICC_RPR_EL1 to normal 0xFF without INTID in initalization?
thanks, and wish you a nice day
Thank you sir,
Use ICC_APxR<n>_EL1 for clearing active priorities is my suitable solution, from your advise.I added extra ICACTIVE and ICPEND in initialization for The explicitly used interrupts. Fortunately, I use PE-self-triggered PPI interrupts, neither 1 of N or LPI is used in the case.Then there have no wrong state in system.
best wishes